Ngày tải lên :
11/05/2014, 14:50
... (s0,A);
not (s1,B);
not (s2,C);
and (Q0,s0,s1,s2);
and (Q1,A,s1,s2);
and (Q2,s0,B,s2);
and (Q3,A,B,s2);
and (Q4,s0,s1,C);
and (Q5,A,s1,C);
and (Q6,s0,B,C);
and (Q7,A,B,C);
endmodule
//*****TESTBENCH*******// ... optimization with
respect to area, performance and/ or power, Layout, Extraction of parasitics and back
annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, ... static
timing analysis, IR drop analysis and crosstalk analysis of the following:
Basic logic gates
CMOS inverter
CMOS NOR/ NAND gates
CMOS XOR and MUX gates
CMOS 1-bit full adder
Static...