central processing unit in computer organization and architecture
William Stallings Computer Organization and Architecture P1
Ngày tải lên :
05/11/2013, 22:15
... module issuing the interrupt?
Đ How do you deal with multiple interrupts?
ã i.e. an interrupt handler being interrupted
Input/Output Problems
Đ Wide variety of peripherals
ã Delivering different ...
free
(Re)Selection
Command,
Data,
Status,
Message
Reset
ISA Bus Interrupt System
Đ ISA bus chains two 8259As together
Đ Link is via interrupt 2
Đ Gives 15 lines
ã 16 lines less one for link
Đ IRQ 9 is ... keyboard
Đ Machine readable
ã Monitoring and control
Đ Communication
ã Modem
ã Network Interface Card (NIC)
Small Computer Systems
Interface (SCSI)
Đ Parallel interface
Đ 8, 16, 32 bit data lines
Đ...
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Tài liệu William Stallings Computer Organization and Architecture P2 pptx
Ngày tải lên :
12/12/2013, 09:15
... programs
ã Swapping
Advantages of Segmentation
Đ Simplifies handling of growing data structures
Đ Allows programs to be altered and recompiled independently,
without re-linking and re-loading
Đ Lends ... process will load into the same place in memory
Đ Instructions contain addresses
ã Locations of data
ã Addresses for instructions (branching)
Đ Logical address - relative to beginning of program
Đ ... process and bring in
another
Đ New process may be smaller than swapped out process
Đ Another hole
Key Elements of O/S
Partitioning
Đ Splitting memory into sections to allocate to processes (including...
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Tài liệu William Stallings Computer Organization and Architecture P4 docx
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12/12/2013, 09:15
... branch
ã Testing data, status of computation (zero, overflow)
ã Branch to some location depending on decision
William Stallings
Computer Organization
and Architecture
Chapter 9
Instruction ... fetch next instruction
ã On most case, next instruction to be fetched immediately
follows current instruction
Specific Data Types
Đ General - arbitrary binary contents
Đ Integer - single binary ... value
Đ Ordinal - unsigned integer
Đ Unpacked BCD - One digit per byte
Đ Packed BCD - 2 BCD digits per byte
Đ Near Pointer - 32 bit offset within segment
Đ Bit field
Đ Byte String
Đ Floating Point
...
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Tài liệu William Stallings Computer Organization and Architecture P5 pptx
Ngày tải lên :
12/12/2013, 09:15
... off between powerful instruction repertoire and saving space
Indirect Addressing Diagram
Address AOpcode
Instruction
Memory
Operand
Pointer to operand
Indirect Addressing (2)
Đ Large address ... programming or compiler writing
ã N.B. C programming
ỹregister int a;
Đ c.f. Direct addressing
Register Addressing (1)
Đ Operand is held in register named in address filed
Đ EA = R
Đ Operand = ... versa
Indirect Addressing (1)
Đ Memory cell pointed to by address field contains the address of
(pointer to) the operand
Đ EA = (A)
ã Look in A, find address (A) and look there for operand
Đ...
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Tài liệu William Stallings Computer Organization and Architecture P6 pptx
Ngày tải lên :
12/12/2013, 09:15
... main memory
Đ Can fetch next instruction during execution of current instruction
Đ Called instruction prefetch
Example Register
Organizations
Data Flow (Data Fetch)
Đ IR is examined
Đ If indirect ... pipeline
Đ Check buffer before fetching from memory
Đ Very good for small loops or jumps
Đ c.f. cache
Đ Used by CRAY-1
Pipelining
Đ Fetch instruction
Đ Decode instruction
Đ Calculate operands ... operands
Đ Execute instructions
Đ Write result
Đ Overlap these operations
Data Flow (Execute)
Đ May take many forms
Đ Depends on instruction being executed
Đ May include
ã Memory read/write
ã Input/Output
ã...
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Computer Organization and Architecture - Chapter 1: Introduction pot
Ngày tải lên :
02/07/2014, 04:21
... average;
SW average
Structure - Top Level
Computer
Main
Memory
Input
Output
Systems
Interconnection
Peripherals
Communication
lines
Central
Processing
Unit
Computer
...
toward a designing a modular
system:
—
Top down
—
Bottom up
William Stallings
Computer Organization
and Architecture
7
th
Edition
Chapter 1
Introduction
Outline of the Book (1)
ã
Computer Evolution ... The CPU
Computer
Arithmetic
and
Login Unit
Control
Unit
Internal CPU
Interconnection
Registers
CPU
I/O
Memory
System
Bus
CPU
Internet Resources
- Web site for book
ã
http://WilliamStallings.com/COA/COA7e.html
links...
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Computer Organization and Architecture phần 1 pps
Ngày tải lên :
14/08/2014, 14:20
...
Computer Organization and Architecture
5th Edition, 2000
by William Stallings
Summary
For junior/senior/graduate-level courses in Computer Organization and Architecture in the Computer ... turn.
Part Three— The central processing unit: The CPU consists of a control unit, registers, the
arithmetic and logic unit, the instruction execution unit, and the interconnections among these ... underlying integrated circuit technology used to construct computer components,
to the increasing use of parallel organization concepts in combining those components.
In spite of the variety and...
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Computer Organization and Architecture phần 2 potx
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14/08/2014, 14:20
... http://www.di.uminho.pt
William Stallings, Computer Organization and Architecture , 5th Ed., 2000
Computer Function (3.2)
ã Processing required for a single instruction is called an instruction ... System Pins - includes clock and reset
Đ Address and Data Pins - 32 time-multiplexed lines for addresses and data,
plus lines to interpret and validate these
Đ Interface Control Pins - control ...
remain pending and are handled sequentially
o Can be handled by prioritizing interrupts, allowing a higher priority interrupt to interrupt
one of lower priority
ã Physical Interrupts
o Interrupts...
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Computer Organization and Architecture phần 3 potx
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14/08/2014, 14:20
...
Universidade do Minho – Dep. Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt
William Stallings, Computer Organization and Architecture, 5th Ed., 2000
Đ Inversely ... do Minho – Dep. Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt
William Stallings, Computer Organization and Architecture, 5th Ed., 2000
ã Chip Packaging ... to signal the initiator that there will not be
new data during the coming cycle. Accordingly, the initiator does not read the data
lines at the beginning of the 5th clock cycle and does not...
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Computer Organization and Architecture phần 4 pptx
Ngày tải lên :
14/08/2014, 14:20
... main memory
and is not present in any other cache
Đ Shared - The line in the cache is the same as that in main memory
and may be present in another cache
Đ Invalid - The line in the cache ... Each line can be in one of 4 states:
Đ Modified - The line in the cache has been modified and is available
only in this cache
Đ Exclusive - The line in the cache is the same as that in main memory ...
Universidade do Minho – Dep. Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt
William Stallings, Computer Organization and Architecture , 5th Ed., 2000
o In a split...
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Computer Organization and Architecture phần 5 pps
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14/08/2014, 14:20
... http://www.di.uminho.pt
William Stallings, Computer Organization and Architecture , 5th Ed., 2000
III. THE CENTRAL PROCESSING UNIT.
8. Computer Arithmetic. (19-Apr-99)
Integer Representation ... Pointers - starting and ending points of the process in memory (used for memory
management
ã Context Data - processor register values
ã The OS maintains state information for each process in ... Minho – Dep. Informática - Campus de Gualtar – 4710-057 Braga - PORTUGAL- http://www.di.uminho.pt
William Stallings, Computer Organization and Architecture , 5th Ed., 2000
o DMA module handles...
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Computer Organization and Architecture phần 6 ppsx
Ngày tải lên :
14/08/2014, 14:20
... IEEE Standard for Floating Point Arithmetic
o Infinity
Đ Most operations involving infinity yield infinity
Đ Signs obey usual laws
Đ -infinity -infinity yields -infinity and +infinity +infinity ... infinity and -infinity
Đ Result is rounded up toward positive infinity or Result is rounded down
toward negative infinity
Đ Useful in implementing interval arithmetic * every calculation in ... loaded into MAR from the control unit
o PC is loaded with address of interrupt routine (so next instruction cycle will begin by
fetching appropriate instruction)
Instruction Pipelining (11.4)...
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