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BAI 1: 1>DFF dong bo rst. library IEEE; use IEEE.STD_LOGIC_1164.all; en$ty DFF_DONGBO is port( CLK : in STD_LOGIC; D : in STD_LOGIC; RST : in STD_LOGIC; Q : out STD_LOGIC ); end DFF_DONGBO; architecture DFF_DONGBO of DFF_DONGBO is begin process(d,clk,rst) begin if (rst='1')and (clk'event and clk='1') then q<='0' ; elsif clk'event and clk='1' then q<=d; end if; end process; end DFF_DONGBO; 2> DFF khong dong bo rst. library IEEE; use IEEE.STD_LOGIC_1164.all; en$ty DFF_KHONGDONGBO is port( D : in STD_LOGIC; RST : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC ); end DFF_KHONGDONGBO; architecture DFF_KHONGDONGBO of DFF_KHONGDONGBO is begin process(d,clk,rst) begin if rst='1' then q<='0'; elsif clk'event and clk='1' then q<=d; end if; end process; end DFF_KHONGDONGBO; 3> RSFF khong dong bo. library IEEE; use IEEE.STD_LOGIC_1164.all; en$ty RSFF is port( R : in STD_LOGIC; S : in STD_LOGIC; CLK : in STD_LOGIC; RST : in STD_LOGIC; Q : out STD_LOGIC ); end RSFF; architecture RSFF of RSFF is signal y: std_logic_vector(1 downto 0); begin process(r,s,clk,rst) variable A: std_logic:='0'; begin y <=r&s; if rst='1' then q<='0'; elsif clk'event and clk='1' then if y="00" then q<=a; elsif y="10" then q<='0' ; elsif y="01" then q<='1' ; elsif y="11" then q<='X'; end if; end if; end process; end RSFF; 4> RSFF dong bo. architecture RSFF_DONGBO of RSFF_DONGBO is signal y: std_logic_vector(1 downto 0); begin process(r,s,clk,rst) variable A: std_logic:='0'; begin y <=r&s; if (rst='1') AND (clk'event and clk='1') then q<='0'; elsif clk'event and clk='1' then if y="00" then q<=a; elsif y="10" then q<='0' ; elsif y="01" then q<='1' ; elsif y="11" then q<='X' ; end if; end if; end process; end RSFF_DONGBO; BAI2: 1> Mach demux 8_1; library IEEE; use IEEE.STD_LOGIC_1164.all; en$ty DEMUX8_1 is port( d : in STD_LOGIC; c: in STD_LOGIC_VECTOR(2 downto 0); Q : out STD_LOGIC_VECTOR(7 downto 0) ); end DEMUX8_1; architecture DEMUX8_1 of DEMUX8_1 is begin process(d,c) begin Q(0)<= D and (not(C(2)) and (not(C(1)) and not(C(0)))); Q(1)<= D and (not(C(2)) and (not(C(1)) and (C(0)))); Q(2)<= D and (not(C(2)) and ((C(1)) and not(C(0)))); Q(3)<= D and (not(C(2)) and ((C(1)) and (C(0)))); Q(4)<= D and ((C(2)) and (not(C(1)) and not(C(0)))); Q(5)<= D and ((C(2)) and (not(C(1)) and (C(0)))); Q(6)<= D and ((C(2)) and ((C(1)) and not(C(0)))); Q(7)<= D and ((C(2)) and ((C(1)) and (C(0)))); end process; end DEMUX8_1; 2> Thiet ke mach giai gray. library IEEE; use IEEE.STD_LOGIC_1164.all; en$ty gm_7seg is port( en : in STD_LOGIC; a : in STD_LOGIC_VECTOR(2 downto 0); b : out STD_LOGIC_VECTOR(2 downto 0) ); end gm_7seg; architecture gm_7seg of gm_7seg is begin process(a,en) begin case A is when "000"=>b<="000"; when"001"=>b<="001"; when"010"=>b<="011"; when"011"=>b<="010"; when "100"=>b<="100"; when"101"=>b<="101"; when"110"=>b<="111"; when"111"=>b<="110"; when others=>b<="XXX"; end case; end process;end gm_7seg; 3>so sanh 2 so nhi phan 4 bit. library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_arith.all; en$ty sscach2 is port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0) ); end sscach2; architecture sscach2 of sscach2 is func$on chuyen (x:in std_logic_vector(3 downto 0))return integer is variable r:integer; begin r:=conv_integer(x(3))*8+ conv_integer(x(2))*4+conv_integer(x(1))*2+conv_integer(x(0)); return r; end chuyen; begin process(a,b) begin if chuyen (a)>chuyen(b)then y<=a; else y<=b; end if; end process; end sscach2; 4. mach giai ma 7 doan. library IEEE; use IEEE.STD_LOGIC_1164.all; en$ty machgiaima7doan is port( a : in STD_LOGIC_VECTOR(3 downto 0); y : out STD_LOGIC_VECTOR(7 downto 0) ); end machgiaima7doan; architecture machgiaima7doan of machgiaima7doan is begin process(a) begin case a is when "0000"=>y<="01000000"; when "0001"=>y<="01111001"; when "0010"=>y<="00100100"; when "0011"=>y<="00110000"; when "0100"=>y<="00011001"; when "0101"=>y<="00010010"; when "0110"=>y<="00000010"; when "0111"=>y<="01111000"; when "1000"=>y<="00000000"; when "1001"=>y<="00010000"; when others =>y<="XXXXXXXX" ; end case; end process; end machgiaima7doan; 5. bo ALU 4 bit; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_arith.all; en$ty ALU is port( A : in STD_LOGIC_VECTOR(3 downto 0); B : in STD_LOGIC_VECTOR(3 downto 0); D : in STD_LOGIC_VECTOR(1 downto 0); Q : out STD_LOGIC_VECTOR(4 downto 0) ); end ALU; architecture ALU of ALU is func$on chuyen(x:in std_logic_vector(3 downto 0)) return integer is variable n: integer; begin n:=conv_integer(x(3))*8+conv_integer(x(2))*4+conv_integer(x(1))*2+conv_integer(x(0)); return n; end chuyen; begin Process(D,A,B) begin if D="00" then cong Q<=conv_std_logic_vector(chuyen(A)+chuyen(B),5); elsif D="01" then Q<=conv_std_logic_vector(chuyen(A)-chuyen(B),5); elsif D="10" then Q<=conv_std_logic_vector(chuyen(A)*chuyen(B),5); else if B="0000" then Q<="XXXXX"; else Q<=conv_std_logic_vector(chuyen(A)/chuyen(B),5); end if; end if; End Process; end ALU; BAI3: 1. DEM TIEN LUI KD=16; library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; en$ty demkd_16_dungconv is port( rst : in STD_LOGIC; clk : in STD_LOGIC; s : in STD_LOGIC; y : out STD_LOGIC_VECTOR(3 downto 0) ); end demkd_16_dungconv; architecture demkd_16_dungconv of demkd_16_dungconv is begin process(s,clk,rst) variable x:integer range 0 to 15:=0; begin if rst='1' then x:=0; elsif clk'event and clk='1' then if s='1' then if x=15 then x:=0; else x:=x+1; end if; else if x=0 then x:=15; else x:=x-1; end if; end if; end if; y<=conv_std_logic_vector(x,4); end process; end demkd_16_dungconv; [...]... mang:std_logic_vector(7 downto 0); variable i:integer:=0; begin if rst='1' then i:=0; elsif clk'event and clk='1' then mang(i):=d; if i=7 then y