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GVHD:Thầy Lê Tuấn Anh Phụ Lục PHỤ LỤC BCODEC 4215ANALOG CHARACTERISTICS(TA=25oC;VA1,VA2,Vd1,VD2 = +5V;Input Levels : Logic 0 = 0V, Logic 1 = VD1,VD2;Full Scale Input Sine wave,No Gain , No Attenuation 1 kHz ; Conversion Rate = 48kHz;No Gain,No Attenuation , SCLK = 3.072MHz , Measurement Bandwidth is 10Hz to 20kHz ; Slave Mode;Unless otherwise specified .)Parameter* Symbol Min Typ Max UnitsAnalog Input Characteristics-Minimum Gain setting(0 dB); Unless otherwise specified .ADC Resolution 16 - - BitsADC Differential Nonlinearity - -±0.9 LSBInstantanneous Dynamic Range :Line Inputs Mic InputsIDR 80728478--dBdBTotal Harmonic Distortion : Line Inputs Mic Inputs THD----0.0120.032%%Interchannel Isolation : Line to Line Inputs Line to Mic Inputs--8060--dBdBInterchannel Gain Mismatch : Line Inputs Mic Inputs----0.50.5dBdBFrequency Respone (Note 1) (0 to 0.45 Fs ) -0.5 - +0.2 dBProgrammable Input Gain: Line Inputs Mic Inputs-0.219.8--23.544dBdBGain Step Size - 1.5 - dBAbsolute Gain Step Error - - 0.75 dBOffset Error Line Inputs (AC coupled)With HPF = 0 Line Inputs (DC coupled)(No Gain) Mic Inputs---±150±10±400±400±150 -LSBOffset Error Line Inputs(AC coupled)With HPF=1 Line Inputs(DC coupled)(No Gain) (Notes 1,2) Mic Inputs---000±5±5±5LSBFull Scale Input Voltage:(MLB=0) Mic Inputs (MLB=1) Mic Inputs Line Inputs0.252.502.500.282.802.800.313.103.10VppVppVppGain Drift - 100 - ppm/oCInput Resistance (Note 3) 20 - - kΩInput Capacitance - - 15 PFCMOUT Output Voltage (Note 4) (maximum output current = 400µA)1.9 2.1 2.3 VNotes :1. This specification is guaranteed by characterization ,not production testing .2. Very low frequency signals will be slightly distorted when using the HPF .3. Input resistance is for the input selected .Non-selected input have a very high (>1MΩ) input resistance .4. DC current only . If dynamic loading exists ,then CMOUT must be buffered or the performance of ADC’s and DAC’s may be degraded . ANALOG CHARACTERISTICS (continued)SVTH:Huỳnh Quốc Trâm 176 GVHD:Thầy Lê Tuấn Anh Phụ Lục Parameter*Symbol Min Typ Max UnitsAnalog Output Characteristics – Minimum Attenuation ;Unless Otherwise Specified DAC Resolution 16 - - BitsDAC Differential Nonlinearity - -±0.9 LSBTotal Dynamic Range TDR - 95 - dBInstantanneous Dynamic Range (OLB=1) (All Outputs)IDR 80 85 - dBTotal Harmonic Distortion: Line Out(Note 5) (OLB = 1) Headphone Out(Note 6) Speaker Out(Note 6) THD------0.0250.2000.320%%%Interchannel Isolation : Line Out(Note 5) Headphone Out(Note 6)--8040--dBdBInterchannel Gain Mismatch : Line Out Headphone----0.50.5dBdBFrequency Respone (Note 1) (0 to 0.45 Fs ) -0.5 - +0.2 dBProgrammable Attenuation (All Outputs) 0.2 - -94.7 dBAttenuation Step Size - 1.5 - dBAbsolute Attenuation Step Error - - 0.75 dBOffset Voltage - 10 - MVFull Scale Output Voltage Line Output (Note 5) with OLB = 0 Headphone Output (Note 6) Speaker Output-Differential (Note 6) 2.553.607.30 2.84.08.03.804.408.80VppVppVppFull Scale Output Voltage Line Output (Note 5) with OLB = 1 Headphone Output (Note 6) Speaker Output-Differential (Note 6)1.81.83.62.02.04.02.22.24.4VppVppVppExternal Load Impedance Line Output Headphone Output Speaker Output104832------ΩΩΩGain Drift - 100 - ppm/oCDeviation from Linear Phase - - 1 DegreeOut of Band Energy(22kHz to 100kHz) Line Out- 60 - dBPower SupplyPower Supply Current (Note7) Operating Power Down --1100.51402mAmAPower Supply Rejection (1kHz)- 40 - dB Notes :5. 10kΩ ,100pF load .Headphone and Speaker outputs disabled .6. 48Ω,100pF load. For the Headphone outputs , THD with 10kΩ ,100pF load is 0.02% .7. Typically ,50% of the power supply current is supplied to the analog power pins(VA1,VA2) and 50% is supplied to the digital power pins (VD1,VD2) .Values given are for unloaded outputs .SVTH:Huỳnh Quốc Trâm 177 GVHD:Thầy Lê Tuấn Anh Phụ Lục A/D DECIMATION FILTER CHARACTERISTICSParameter*Symbol Min Typ Max UnitsPassband (Fs is conversion freq.) 0 - 0.45Fs HzFrequency Respone -0.5 - +0.2 dBPassband Ripple - -±0.1 dBTransition Band 0.45Fs - 0.55Fs HzStop Band≥0.55Fs - - HzStop Band Rejection 74 - - dBGroup Delay 16Fs - sGroup Delay Variation vs. Frequency - 0µsD/A INTERPOLATON FILTER CHARACTERISTICSParameter*SymbolMin Typ Max UnitsPassband (Fs is conversion freq.) 0 - 0.45Fs HzFrequency Respone -0.5 - +0.2 dBPassband Ripple - -±0.1 dBTransition Band 0.45Fs - 0.55Fs HzStop Band≥0.55Fs - - HzStop Band Rejection 74 - - dBGroup Delay 16Fs - sGroup Delay Variation vs. Frequency - 0.1FsµsDIGITAL CHARACTERISTICS(TA=25oC ;VA1,VA2,VD1,VD2 = 5V)Parameter*Symbol Min Max UnitsHigh-level Input VoltageVIH(VD1,VD2)-1.0 (VD1,VD2)+0.3 VLow-level Input VoltageVIL-0.3 1.0 VHigh-level Output Voltage at I0=2.0mAVOH(VD1,VD2)-0.2 - VLow-level Output Voltage atI0=2.0mAVOL- 0.1 VInput Leakage Current (Digital Inputs) - 10AµOutput Leakage Current (High-Z Digital Outputs)- 10AµSVTH:Huỳnh Quốc Trâm 178 GVHD:Thầy Lê Tuấn Anh Phụ Lục SWITCHING CHARACTERISTICS(TA=25oC ;VA1,VA2,VD1,VD2 = +5V ,outputs loaded with 30pF ;Inputs Level ; Logic 0 = 0V , Logic 1 =VD1,VD2 )Parameter*Symbol Min Typ Max UnitsSCLK period Master Mode,XCLK=1(Note 8) Slave Mode(XCLK=0)tsckwtsckw-801/(Fs*bpt)---snsSCLK high time Slave Mode,XCLK =0(Note9)tsckh25 - - nsSCLK low time Slave Mode,XCLK =0(Note9)tsckl25 - - nsInput Setup Timetsl15 - - nsInput Hold Timethl10 - - nsInput Transition Time (10% to 90% points) - - 10 nsOutput delay t1pd- - 28 nsSCLK to TSOUTt2pd- - 30 nsOutput to Hi-Z state Time Slot 8 , Bit 0thz- - 12 nsOutput to non Hi-Z Time Slot 1 , Bit 7tnz15 - - nsInput Clock Frequency Crystals CLKIN (note 10)-1.204--2713.5MhzMhzInput clock (CLKIN) low time 30 - - nsInput clock (CLKIN) high time 30 - - nsSample rate Fs 4 - 50 KHzRESET low time (Note 11)500 - - ns8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf) ,the SCLK duty cycle is 50% . When BSEL1,0 is set to 256 bpf , SCLK will have the same duty cycle as CLKOUT . See Internal Clock Generation section .9. In Slave Mode ,FSYNC and SCLK must bederived from the master clock running the codec (CLKIN , XTAL1,XTAL2) .10. Sample rate specifications must not be exceeded .11. After powering up the CS4215 ,RESET should be held low for 50 ms to allow the voltage reference to settle .SVTH:Huỳnh Quốc Trâm 179 GVHD:Thầy Lê Tuấn Anh Phụ Lục ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V)Parameter Symbol Min Max UnitsPower Supplies : Digital AnalogVD1,VD2VA1,VA2-0.3-0.36.06.0VVInput Current (Except Supply Pins) - mAAnalog Input Voltage -0.3 VDigital Input Voltage -0.3 VAmbient Temperature (Power Aplied) -55OCStorage Temperature -65OCWarning : Operating beyond these limits may result in permanent damage to the device . Normal operaion is not guaranteed at these extremex .RECOMMEND OPERATING CONDITIONS (AGND , DGND = 0V all voltages with respect to 0V) .Parameter Symbol Min Max UnitsPower Supplies : Digital (Note 8) Analog (Note 8)VD1,VD2VA1,VA24.754.755.05.0VVOperating Ambient TemperatureTA0 25ocNote : 8. VAVD − must be less than 0.5Volts (one diode drop) .SVTH:Huỳnh Quốc Trâm 180 GVHD:Thầy Lê Tuấn Anh Phụ Lục DSP56002Data Sheet ConventionsThis data sheet uses the following conventions :•OVERBARS are used to indicate a signal that is active when pulled to ground (see Table 1)e.g. the HREQ pin is active when pulled to ground . Therefore , references to the HREQ pin will always have an overbar .• The word “assert” (see Table 1) means that a high true (active high ) signal is puulled high to VCC or that a low true (active low) signal is pulled low to ground .• The word “deassert” (see Table 1) means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC .Table 1 High True / Low True Signal ConventionsSignal / Symbol Logic State Signal State VoltagePINTrue Asserted Ground PINFalse Deasserted VCCPIN True Asserted VCCPIN False Deasserted Ground NOTES :1. PIN is a generic term for any pin on the chip .2. Ground is an acceptable low voltage level . See the DC electrical specifications for the range of acceptable low voltage levels (typically a TTL logic low) .3. VCC is an acceptable high voltage level . See the DC electrical specifications for the range of acceptable high voltge levels (typically a TTL logic high) .SVTH:Huỳnh Quốc Trâm 181 GVHD:Thầy Lê Tuấn Anh Phụ Lục Pin GroupingsThe input and output signals of the DSP56002 are organized into functional groups as shown in Table 2 .Table 2 DSP56002 functional Pin GroupingsFunctional Group Number of PinsAddress Bus 16Data Bus 24Bus Control 10Host Interface (HI) 15Serial Communication Interface (SCI) 3Synchronous Serial Interface (SSI) 6Timer /Event Counter 1Interrupt and Mode Control 4Phase-Locked Loop(PLL) and Clock 7On-chip Emulation (OnCETM) Port4Power (VCC) 16Ground (GND) 24Reserved (no connect) 2Total Number of Pins 132* alternately , general purpose I/O pins** package dependentSVTH:Huỳnh Quốc Trâm 182 GVHD:Thầy Lê Tuấn Anh Phụ Lục Electrical Specifications DSP56002 ( 5.0 Volt Operation)The DSP56002 is fabricated in high desity CMOS with TTL compatible inputs and outputs .Table 3 Absolute Maximum Ratings (GND = 0 Vdc)Rating Symbol Value UnitSupply Voltage VCC -0.3 to +7.0 VAll Input Voltages VINGND –0.5 toVCC +0.5VCurrent Drain per Pin Excluding VCC and GNDI 10 mAOperating Temperature RangeTJ-40 to +105oCStorage TemperatureT stg-55 to +1500CTable 4 Thermal Characteristics of PackagesThermalResistancePQFPSymbol Value Units Symbol Value Units Symbol Value UnitsJunctiontoAmbientJAθ38oC/WJAθ22oC/WJAθ49oC/WJunctionto Case (estimated)JCθ13oC/WJCθ6.5oC/WJCθ12oC/WSVTH:Huỳnh Quốc Trâm 183 GVHD:Thầy Lê Tuấn Anh Phụ Lục DSP56002 DC Electrical Characteristics ( VCC =5.0 Vdc±10% ; TJ = -40o to +105oC) Table 5 DC Electrical Characteristics for the DSP56002Characteristics Symbol DSP56002Min Typ MaxUnitsSupply Voltage VCC 4.5 5.0 5.5 VInput High Voltage•Except EXTAL , RESET, MODA , MODB , MODC•EXTAL•RESET•MODA , MODB , MODCVIHVIHCVIHRVIHM2.04.02.53.5----VCCVCCVCCVCCVVVVInput Low Voltage•Except EXTAL ,MODA,MODB,MODC•EXTAL•MODA , MODB , MODCVILVILCVILM-0.5-0.5-0.5---0.80.62.0VVVInput Leakage Current EXTAL, RESET,IRQA/MODA, MODB/IRQB, MODC/NMI,BR,WTIIN-1 - 1AµThree-State(Off-State) Input Current (@2.4V / 0.4V)ITSI-10 - 10AµOutput High Voltage(IOH = -0.4mA) VOH2.4 - - VOutput Low Voltage(IOL = 3mA ;HREQ IOL = 6.7mA,TXD IOL = 6.7mA)VOL- - 0.4 VInternal Supply Current at 40MHz (See Note3) • in Wait Mode (See Note 1) • in Stop Mode (See Note 1)ICCI ICCWICCS---901221052095mAmAAµInternal Supply Current at 66MHz(See Note3) • in Wait Mode (See Note 1) • in Stop Mode (See Note 1)ICCI ICCWICCS---951521302595mAmAAµPLL Supply Current (See Note 4 ) at 40MHz at 66MHz--11.11.51.5mAmACKOUT Supply Current at 40MHz(See Note 5) at 66MHz--14282035mAmAInput Capacitance (See Note 2) CIN- 10 - pFNotes : 1. In order to obtain these results all inputs must be terminated (i.e., not allowed to float) using CMOS level.2. Periodically sampled and not 100% tested. 3. Power Consumption in the Design Considerations section describes how to calculate the external supply current.4. Value given are for PLL enabled.5. Value given are for CKOUT enable.SVTH:Huỳnh Quốc Trâm 184 GVHD:Thầy Lê Tuấn Anh Phụ Lục AC Electrical Characteristics The timing waveforms in the AC Electricl Characteristics are tested with a VIL maximum of 0.5V and a VIH minimum of 2.4V for all pins, except EXTAL, RESET , MODA, MODB, and MODC. These four pins are tested using the input levels set forth in the DC Electrical Characteristics section. AC timing specifications which are referenced to a device input signal aremeasured in production with respect to the 50% point of the respective input signal‘s transition. DSP56002 output levels are measured with the producion test machine VOL and VOH reference level set at 0.8 V and 2.0 V respectively.Internal ClocksFor each occurrence of TH, TL,TC or ICYC substitube with the expressions given in Table 6 .ETH, ETL, and ETC are further defined in the Table 7. DF and MF are PLL devision and multiplication factors set registers.Table 6 Internal ClocksCharacteristics Symbol ExpressionInternal Operation Frequency fInternal Clock High Period- with PLL disabled - with PLL enabled and MF≤4- with PLL enabled and MF >4 THETH(Min) 0.48 x ETC x DF/MF(Max) 0.52 x ETC x DF/MF(Min) 0.467 x ETC x DF/MF(Max) 0.533 x ETC x DF/MFInternal Clock Low Period- with PLL disabled - with PLL enabled and MF≤4- with PLL enabled and MF >4TLETL(Min) 0.48 x ETC x DF/MF(Max) 0.52 x ETC x DF/MF(Min) 0.467 x ETC x DF/MF(Max) 0.533 x ETC x DF/MFInternal Clock Cycle Time TC ETC x DF/MFIntruction Cycle Time ICYC2 x TCSVTH:Huỳnh Quốc Trâm 185 [...]... interrupt and IRQA and IRQB are defined as level – sensitive, then timings 19 through 22 apply to prevent multiple interrupt service To avoid these timing restrictions, the deassertive edge-triggered mode is recommended when using fast interrupt Long interrupts are recommended when using level-sensitive mode SVTH:Huỳnh Quốc Trâm 190 GVHD:Thầy Lê Tuấn Anh Phụ Lục Host I/O Timing VCC = 5.0 Vdc ± 10%, TJ... After HEN Deassertion SVTH:Huỳnh Quốc Trâm Max TC+31 26 13 13 2 x TC + 31 2 x TC + 31 - ns 4 - ns 3 - ns 0 - ns - 26 ns - 18 ns 2.5 - ns 0 - ns 3 - ns 0 3 0 - ns ns ns 3 - ns ns ns ns 191 GVHD:Thầy Lê Tuấn Anh 15 16 17 18 19 DMA HACK Assertion to HREQ Deassertion (See Note 4) DMA HACK Deassertion to HREQ Assertion (See Notes 4, 5) • for DMA RXL Read • for DMA RXL Write • all other cases Delay from HEN... x ck i ck a x ck i ck a i ck s x ck i ck x ck i ck a ns Max 4 x TC 3 x TC TSSICC/2-10.8 TC + TL TSSICC/2-10.8 TC + TL 3.3 15.8 13 18 3.3 0.8 17.4 Unit ns ns ns ns ns ns ns ns ns 194 GVHD:Thầy Lê Tuấn Anh 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FSR Input (wl) High Before RXC Falling Edge FSR Input (bl) Hold Time After RXC Falling Edge Flags Input Setup Before RXC Falling Edge Flags Input Hold... Instruction is: • Single Cycle • Two Cycles (See Note 3) Synchronous Interrupt Setup Time from IRQA, IRQB, NMI Assertion to the CKOUT transition #2 SVTH:Huỳnh Quốc Trâm 10 ns 189 GVHD:Thầy Lê Tuấn Anh 17 18 19 20 21 Synchronous Interrupt Delay Time from the CKOUT transition #2 to the First External Address Output Valid caused by the First Instruction Fetch after coming out of Wait State Duration for IRQA... corresponding status bits or HREQ 4 HREQ is pulled up by a 1K Ω resistor 5 Specifications are periodically sampled and not 100% tested 6 May decrease to 0 ns for future versions SVTH:Huỳnh Quốc Trâm 192 GVHD:Thầy Lê Tuấn Anh Phụ Lục Serial Communication Interface(SCI) Timing VCC = 5.0 Vdc ± 10%, TJ = -40oC to +105oC, CL = 50pF + 2 TTL Loads TSCC = Synchronous Clock Cycle Time (for internal clock,... ns 4 5 < intentionally blank> Output Data Setup to Clock Rising Edge (Internal Clock) Output Data Hold After Clock Rising Edge (Internal Clock) tACC/2 – 51 - ns tACC/2 – 51 - ns 6 SVTH:Huỳnh Quốc Trâm 193 GVHD:Thầy Lê Tuấn Anh Phụ Lục Synchronous Serial Interface (SSI) Timing VCC = 5.0 Vdc ± 10%, TJ = -40oC to +105oC, CL = 50pF + 2 TTL Loads tSSIC = SSI clock cycle time TXC(SCK pin) = Transmit Clock... PLL disabled • with PLL enabled Ef Max 66 MHz Min Unit Max ETC ICYC 0 66 ∞ 7.09 ∞ 10.5 235.5 µ s 6.36 235.5 µ s 11.7 ∞ 7.09 ∞ 10.5 ETL 40 11.7 ETH 0 235.5 µ s 6.36 235.5 µ s 25 25 ∞ 235.5 µ s 50 50 MHz 819. 2 µ s 7.09 6.36 ∞ 235.5 µ s ∞ ns ns ns ns NOTE: External Clock Input High and External Clock Input Low are measured at 50% of the input transition Phase-Locked Loop (PLL) SVTH:Huỳnh Quốc Trâm 187 GVHD:Thầy... ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTE: 1 For internal clock, External Clock Cycle is defined by ICYC and SSI control register 2 Periodically sampled, and not 100% tested SVTH:Huỳnh Quốc Trâm 195 . Inputs Mic Inputs-0. 219. 8--23.544dBdBGain Step Size - 1.5 - dBAbsolute Gain Step Error - - 0.75 dBOffset. Time = ICYC = 2 x TC (See Note)• with PLL disabled• with PLL enabledICYC5050∞ 819. 2µsnsNOTE: External Clock Input High and External Clock Input Low are measured