Ebook Digital integrated circuits prentice hall: Part 1

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(BQ) Part 1 book Digital integrated circuits prentice hall has contents: Introduction, the manufacturing process, the devices, the devices, the cmos inverter. chapter1.fm Page Friday, January 18, 2002 8:58 AM CHAPTER INTRODUCTION The evolution of digital circuit design n Compelling issues in digital circuit design n How to measure the quality of a design n Valuable references 1.1 A Historical Perspective 1.2 Issues in Digital Integrated Circuit Design 1.3 Quality Metrics of a Digital Design 1.4 Summary 1.5 To Probe Further chapter1.fm Page 10 Friday, January 18, 2002 8:58 AM 10 1.1 INTRODUCTION Chapter A Historical Perspective The concept of digital data manipulation has made a dramatic impact on our society One has long grown accustomed to the idea of digital computers Evolving steadily from mainframe and minicomputers, personal and laptop computers have proliferated into daily life More significant, however, is a continuous trend towards digital solutions in all other areas of electronics Instrumentation was one of the first noncomputing domains where the potential benefits of digital data manipulation over analog processing were recognized Other areas such as control were soon to follow Only recently have we witnessed the conversion of telecommunications and consumer electronics towards the digital format Increasingly, telephone data is transmitted and processed digitally over both wired and wireless networks The compact disk has revolutionized the audio world, and digital video is following in its footsteps The idea of implementing computational engines using an encoded data format is by no means an idea of our times In the early nineteenth century, Babbage envisioned largescale mechanical computing devices, called Difference Engines [Swade93] Although these engines use the decimal number system rather than the binary representation now common in modern electronics, the underlying concepts are very similar The Analytical Engine, developed in 1834, was perceived as a general-purpose computing machine, with features strikingly close to modern computers Besides executing the basic repertoire of operations (addition, subtraction, multiplication, and division) in arbitrary sequences, the machine operated in a two-cycle sequence, called “store” and “mill” (execute), similar to current computers It even used pipelining to speed up the execution of the addition operation! Unfortunately, the complexity and the cost of the designs made the concept impractical For instance, the design of Difference Engine I (part of which is shown in Figure 1.1) required 25,000 mechanical parts at a total cost of £17,470 (in 1834!) Figure 1.1 Working part of Babbage’s Difference Engine I (1832), the first known automatic calculator (from [Swade93], courtesy of the Science Museum of London) chapter1.fm Page 11 Friday, January 18, 2002 8:58 AM Section 1.1 A Historical Perspective 11 The electrical solution turned out to be more cost effective Early digital electronics systems were based on magnetically controlled switches (or relays) They were mainly used in the implementation of very simple logic networks Examples of such are train safety systems, where they are still being used at present The age of digital electronic computing only started in full with the introduction of the vacuum tube While originally used almost exclusively for analog processing, it was realized early on that the vacuum tube was useful for digital computations as well Soon complete computers were realized The era of the vacuum tube based computer culminated in the design of machines such as the ENIAC (intended for computing artillery firing tables) and the UNIVAC I (the first successful commercial computer) To get an idea about integration density, the ENIAC was 80 feet long, 8.5 feet high and several feet wide and incorporated 18,000 vacuum tubes It became rapidly clear, however, that this design technology had reached its limits Reliability problems and excessive power consumption made the implementation of larger engines economically and practically infeasible All changed with the invention of the transistor at Bell Telephone Laboratories in 1947 [Bardeen48], followed by the introduction of the bipolar transistor by Schockley in 1949 [Schockley49]1 It took till 1956 before this led to the first bipolar digital logic gate, introduced by Harris [Harris56], and even more time before this translated into a set of integrated-circuit commercial logic gates, called the Fairchild Micrologic family [Norman60] The first truly successful IC logic family, TTL (Transistor-Transistor Logic) was pioneered in 1962 [Beeson62] Other logic families were devised with higher performance in mind Examples of these are the current switching circuits that produced the first subnanosecond digital gates and culminated in the ECL (Emitter-Coupled Logic) family [Masaki74] TTL had the advantage, however, of offering a higher integration density and was the basis of the first integrated circuit revolution In fact, the manufacturing of TTL components is what spear-headed the first large semiconductor companies such as Fairchild, National, and Texas Instruments The family was so successful that it composed the largest fraction of the digital semiconductor market until the 1980s Ultimately, bipolar digital logic lost the battle for hegemony in the digital design world for exactly the reasons that haunted the vacuum tube approach: the large power consumption per gate puts an upper limit on the number of gates that can be reliably integrated on a single die, package, housing, or box Although attempts were made to develop high integration density, low-power bipolar families (such as I2L—Integrated Injection Logic [Hart72]), the torch was gradually passed to the MOS digital integrated circuit approach The basic principle behind the MOSFET transistor (originally called IGFET) was proposed in a patent by J Lilienfeld (Canada) as early as 1925, and, independently, by O Heil in England in 1935 Insufficient knowledge of the materials and gate stability problems, however, delayed the practical usability of the device for a long time Once these were solved, MOS digital integrated circuits started to take off in full in the early 1970s Remarkably, the first MOS logic gates introduced were of the CMOS variety [Wanlass63], and this trend continued till the late 1960s The complexity of the manufacturing process delayed the full exploitation of these devices for two more decades Instead, An intriguing overview of the evolution of digital integrated circuits can be found in [Murphy93] (Most of the data in this overview has been extracted from this reference) It is accompanied by some of the historically ground-breaking publications in the domain of digital IC’s chapter1.fm Page 12 Friday, January 18, 2002 8:58 AM 12 INTRODUCTION Chapter the first practical MOS integrated circuits were implemented in PMOS-only logic and were used in applications such as calculators The second age of the digital integrated circuit revolution was inaugurated with the introduction of the first microprocessors by Intel in 1972 (the 4004) [Faggin72] and 1974 (the 8080) [Shima74] These processors were implemented in NMOS-only logic, which has the advantage of higher speed over the PMOS logic Simultaneously, MOS technology enabled the realization of the first highdensity semiconductor memories For instance, the first 4Kbit MOS memory was introduced in 1970 [Hoff70] These events were at the start of a truly astounding evolution towards ever higher integration densities and speed performances, a revolution that is still in full swing right now The road to the current levels of integration has not been without hindrances, however In the late 1970s, NMOS-only logic started to suffer from the same plague that made high-density bipolar logic unattractive or infeasible: power consumption This realization, combined with progress in manufacturing technology, finally tilted the balance towards the CMOS technology, and this is where we still are today Interestingly enough, power consumption concerns are rapidly becoming dominant in CMOS design as well, and this time there does not seem to be a new technology around the corner to alleviate the problem Although the large majority of the current integrated circuits are implemented in the MOS technology, other technologies come into play when very high performance is at stake An example of this is the BiCMOS technology that combines bipolar and MOS devices on the same die BiCMOS is used in high-speed memories and gate arrays When even higher performance is necessary, other technologies emerge besides the already mentioned bipolar silicon ECL family—Gallium-Arsenide, Silicon-Germanium and even superconducting technologies These technologies only play a very small role in the overall digital integrated circuit design scene With the ever increasing performance of CMOS, this role is bound to be further reduced with time Hence the focus of this textbook on CMOS only 1.2 Issues in Digital Integrated Circuit Design Integration density and performance of integrated circuits have gone through an astounding revolution in the last couple of decades In the 1960s, Gordon Moore, then with Fairchild Corporation and later cofounder of Intel, predicted that the number of transistors that can be integrated on a single die would grow exponentially with time This prediction, later called Moore’s law, has proven to be amazingly visionary [Moore65] Its validity is best illustrated with the aid of a set of graphs Figure 1.2 plots the integration density of both logic IC’s and memory as a function of time As can be observed, integration complexity doubles approximately every to years As a result, memory density has increased by more than a thousandfold since 1970 An intriguing case study is offered by the microprocessor From its inception in the early seventies, the microprocessor has grown in performance and complexity at a steady and predictable pace The transistor counts for a number of landmark designs are collected in Figure 1.3 The million-transistor/chip barrier was crossed in the late eighties Clock frequencies double every three years and have reached into the GHz range This is illus- chapter1.fm Page 13 Friday, January 18, 2002 8:58 AM Section 1.2 Issues in Digital Integrated Circuit Design 13 64 Gbits *0.08µm 1010 Human memory Human memory Human DNA Human DNA 109 Gbits Gbits Number of bits per chip 108 256 Mbits 107 64 Mbits 106 Book Book 16 Mbits Mbits 105 Mbits 104 256 Kbits 0.15µm 0.15-0.2µm 0.25-0.3µm 0.35-0.4µm 0.5-0.6µm 0.7-0.8µm 1.0-1.2µm 1.6-2.4µm 64 Kbits Encyclopedia Encyclopedia hrs CD Audio hrs CD Audio 30 30sec secHDTV HDTV Page Page 1970 1980 1990 2000 2010 Year (b) Trends in memory complexity (a) Trends in logic IC complexity Figure 1.2 Evolution of integration complexity of logic ICs and memories as a function of time trated in Figure 1.4, which plots the microprocessor trends in terms of performance at the beginning of the 21st century An important observation is that, as of now, these trends have not shown any signs of a slow-down It should be no surprise to the reader that this revolution has had a profound impact on how digital circuits are designed Early designs were truly hand-crafted Every transistor was laid out and optimized individually and carefully fitted into its environment This is adequately illustrated in Figure 1.5a, which shows the design of the Intel 4004 microprocessor This approach is, obviously, not appropriate when more than a million devices have to be created and assembled With the rapid evolution of the design technology, time-to-market is one of the crucial factors in the ultimate success of a component 100000000 Pentium Pentium III Pentium II Transistors 10000000 Pentium ® 1000000 486 386 100000 286 ™ 8086 10000 4004 1000 1970 8080 8008 1975 1980 1985 1990 1995 2000 Year of Introduction Figure 1.3 Historical evolution of microprocessor transistor count (from [Intel01]) chapter1.fm Page 14 Friday, January 18, 2002 8:58 AM 14 INTRODUCTION Chapter 10000 Doubles every years Frequency (Mhz) 1000 P6 100 Pentium ® proc 486 10 8086 8085 0.1 1970 286 386 8080 8008 4004 1980 1990 Year 2000 2010 Figure 1.4 Microprocessor performance trends at the beginning of the 21st century Designers have, therefore, increasingly adhered to rigid design methodologies and strategies that are more amenable to design automation The impact of this approach is apparent from the layout of one of the later Intel microprocessors, the Pentium® 4, shown in Figure 1.5b Instead of the individualized approach of the earlier designs, a circuit is constructed in a hierarchical way: a processor is a collection of modules, each of which consists of a number of cells on its own Cells are reused as much as possible to reduce the design effort and to enhance the chances for a first-time-right implementation The fact that this hierarchical approach is at all possible is the key ingredient for the success of digital circuit design and also explains why, for instance, very large scale analog design has never caught on The obvious next question is why such an approach is feasible in the digital world and not (or to a lesser degree) in analog designs The crucial concept here, and the most important one in dealing with the complexity issue, is abstraction At each design level, the internal details of a complex module can be abstracted away and replaced by a black box view or model This model contains virtually all the information needed to deal with the block at the next level of hierarchy For instance, once a designer has implemented a multiplier module, its performance can be defined very accurately and can be captured in a model The performance of this multiplier is in general only marginally influenced by the way it is utilized in a larger system For all purposes, it can hence be considered a black box with known characteristics As there exists no compelling need for the system designer to look inside this box, design complexity is substantially reduced The impact of this divide and conquer approach is dramatic Instead of having to deal with a myriad of elements, the designer has to consider only a handful of components, each of which are characterized in performance and cost by a small number of parameters This is analogous to a software designer using a library of software routines such as input/output drivers Someone writing a large program does not bother to look inside those library routines The only thing he cares about is the intended result of calling one of those modules Imagine what writing software programs would be like if one had to fetch every bit individually from the disk and ensure its correctness instead of relying on handy “file open” and “get string” operators chapter1.fm Page 15 Friday, January 18, 2002 8:58 AM Section 1.2 Issues in Digital Integrated Circuit Design 15 (a) The 4004 microprocessor Standard Cell Module Memory Module (b) The Pentium ® microprocessor Figure 1.5 Comparing the design methodologies of the Intel 4004 (1971) and Pentium ® (2000 microprocessors (reprinted with permission from Intel) chapter1.fm Page 16 Friday, January 18, 2002 8:58 AM 16 INTRODUCTION Chapter Typically used abstraction levels in digital circuit design are, in order of increasing abstraction, the device, circuit, gate, functional module (e.g., adder) and system levels (e.g., processor), as illustrated in Figure 1.6 A semiconductor device is an entity with a SYSTEM MODULE + GATE CIRCUIT DEVICE G D S n Figure 1.6 + n + Design abstraction levels in digital circuits very complex behavior No circuit designer will ever seriously consider the solid-state physics equations governing the behavior of the device when designing a digital gate Instead he will use a simplified model that adequately describes the input-output behavior of the transistor For instance, an AND gate is adequately described by its Boolean expression (Z = A.B), its bounding box, the position of the input and output terminals, and the delay between the inputs and the output This design philosophy has been the enabler for the emergence of elaborate computer-aided design (CAD) frameworks for digital integrated circuits; without it the current design complexity would not have been achievable Design tools include simulation at the various complexity levels, design verification, layout generation, and design synthesis An overview of these tools and design methodologies is given in Chapter of this textbook Furthermore, to avoid the redesign and reverification of frequently used cells such as basic gates and arithmetic and memory modules, designers most often resort to cell libraries These libraries contain not only the layouts, but also provide complete documentation and characterization of the behavior of the cells The use of cell libraries is, for chapter1.fm Page 17 Friday, January 18, 2002 8:58 AM Section 1.2 Issues in Digital Integrated Circuit Design 17 instance, apparent in the layout of the Pentium ® processor (Figure 1.5b) The integer and floating-point unit, just to name a few, contain large sections designed using the socalled standard cell approach In this approach, logic gates are placed in rows of cells of equal height and interconnected using routing channels The layout of such a block can be generated automatically given that a library of cells is available The preceding analysis demonstrates that design automation and modular design practices have effectively addressed some of the complexity issues incurred in contemporary digital design This leads to the following pertinent question If design automation solves all our design problems, why should we be concerned with digital circuit design at all? Will the next-generation digital designer ever have to worry about transistors or parasitics, or is the smallest design entity he will ever consider the gate and the module? The truth is that the reality is more complex, and various reasons exist as to why an insight into digital circuits and their intricacies will still be an important asset for a long time to come • First of all, someone still has to design and implement the module libraries Semiconductor technologies continue to advance from year to year Until one has developed a fool-proof approach towards “porting” a cell from one technology to another, each change in technology—which happens approximately every two years—requires a redesign of the library • Creating an adequate model of a cell or module requires an in-depth understanding of its internal operation For instance, to identify the dominant performance parameters of a given design, one has to recognize the critical timing path first • The library-based approach works fine when the design constraints (speed, cost or power) are not stringent This is the case for a large number of application-specific designs, where the main goal is to provide a more integrated system solution, and performance requirements are easily within the capabilities of the technology Unfortunately for a large number of other products such as microprocessors, success hinges on high performance, and designers therefore tend to push technology to its limits At that point, the hierarchical approach tends to become somewhat less attractive To resort to our previous analogy to software methodologies, a programmer tends to “customize” software routines when execution speed is crucial; compilers—or design tools—are not yet to the level of what human sweat or ingenuity can deliver • Even more important is the observation that the abstraction-based approach is only correct to a certain degree The performance of, for instance, an adder can be substantially influenced by the way it is connected to its environment The interconnection wires themselves contribute to delay as they introduce parasitic capacitances, resistances and even inductances The impact of the interconnect parasitics is bound to increase in the years to come with the scaling of the technology • Scaling tends to emphasize some other deficiencies of the abstraction-based model Some design entities tend to be global or external (to resort anew to the software analogy) Examples of global factors are the clock signals, used for synchronization in a digital design, and the supply lines Increasing the size of a digital design has a chapter1.fm Page 18 Friday, January 18, 2002 8:58 AM 18 INTRODUCTION Chapter profound effect on these global signals For instance, connecting more cells to a supply line can cause a voltage drop over the wire, which, in its turn, can slow down all the connected cells Issues such as clock distribution, circuit synchronization, and supply-voltage distribution are becoming more and more critical Coping with them requires a profound understanding of the intricacies of digital circuit design • Another impact of technology evolution is that new design issues and constraints tend to emerge over time A typical example of this is the periodical reemergence of power dissipation as a constraining factor, as was already illustrated in the historical overview Another example is the changing ratio between device and interconnect parasitics To cope with these unforeseen factors, one must at least be able to model and analyze their impact, requiring once again a profound insight into circuit topology and behavior • Finally, when things can go wrong, they A fabricated circuit does not always exhibit the exact waveforms one might expect from advance simulations Deviations can be caused by variations in the fabrication process parameters, or by the inductance of the package, or by a badly modeled clock signal Troubleshooting a design requires circuit expertise For all the above reasons, it is my belief that an in-depth knowledge of digital circuit design techniques and approaches is an essential asset for a digital-system designer Even though she might not have to deal with the details of the circuit on a daily basis, the understanding will help her to cope with unexpected circumstances and to determine the dominant effects when analyzing a design Example 1.1 Clocks Defy Hierarchy To illustrate some of the issues raised above, let us examine the impact of deficiencies in one of the most important global signals in a design, the clock The function of the clock signal in a digital design is to order the multitude of events happening in the circuit This task can be compared to the function of a traffic light that determines which cars are allowed to move It also makes sure that all operations are completed before the next one starts—a traffic light should be green long enough to allow a car or a pedestrian to cross the road Under ideal circumstances, the clock signal is a periodic step waveform with transitions synchronized throughout the designed circuit (Figure 1.7a) In light of our analogy, changes in the traffic lights should be synchronized to maximize throughput while avoiding accidents The importance of the clock alignment concept is illustrated with the example of two cascaded registers, both operating on the rising edge of the clock φ (Figure 1.7b) Under normal operating conditions, the input In gets sampled into the first register on the rising edge of φ and appears at the output exactly one clock period later This is confirmed by the simulations shown in Figure 1.8c (signal Out) Due to delays associated with routing the clock wires, it may happen that the clocks become misaligned with respect to each other As a result, the registers are interpreting time indicated by the clock signal differently Consider the case that the clock signal for the second register is delayed—or skewed—by a value δ The rising edge of the delayed clock φ′ will postpone the sampling of the input of the second register If the time it takes to propagate the output of the first register to the input of the second is smaller than the clock delay, the latter will sample the wrong value This causes the output to change prematurely, as clearly illustrated in the simulation, where the signal Out′ goes high at the first rising edge of φ′ instead of chapter5.fm Page 225 Friday, January 18, 2002 9:01 AM Section 5.6 Perspective: Technology Scaling and its Impact on the Inverter Metrics 225 ∝ S2 Figure 5.40 Evolution of power-density in micro- and DSP processors, as a function of the scaling factor S ([Sakurai97]) S is normalized to for a µm process S Table 5.5 Scaling scenarios for wire capacitance S and U represent the technology and voltage scaling parameters, respectively, while SL stands for the wire-length scaling factor εc represents the impact of fringing and inter-wire capacitances Parameter Relation General Scaling Wire Capacitance WL/t εc/SL Wire Delay RonCint εc/SL Wire Energy CintV2 εc/SLU2 Wire Delay / Intrinsic Delay εcS/SL Wire Energy / Intrinsic Energy εcS/SL The model predicts that the interconnect-caused delay (and energy) gain in importance with the scaling of technology This impact is limited to an increase with εc for short wires (S = SL), but it becomes increasingly more outspoken for medium-range and long wires (SL < S) These conclusions have been confirmed by a number of studies, an example of which is shown in Figure 5.41 How the ratio of wire over intrinsic contributions will actually evolve is debatable, as it depends upon a wide range of independent parameters such as system architecture, design methodology, transistor sizing, and interconnect materials The doom-day scenario that interconnect may cause CMOS performance to saturate in the very near future hence may be exaggerated Yet, it is clear to that increased attention to interconnect is an absolute necessity, and may change the way the next-generation circuits are designed and optimized (e.g [Sylvester99]) chapter5.fm Page 226 Friday, January 18, 2002 9:01 AM 226 THE CMOS INVERTER Chapter Figure 5.41 Evolution of wire delay / gate delay ratio with respect to technology (from [Fisher98]) 5.7 Summary This chapter presented a rigorous and in-depth analysis of the static CMOS inverter The key characteristics of the gate are summarized: • The static CMOS inverter combines a pull-up PMOS section with a pull-down NMOS device The PMOS is normally made wider than the NMOS due to its inferior current-driving capabilities • The gate has an almost ideal voltage-transfer characteristic The logic swing is equal to the supply voltage and is not a function of the transistor sizes The noise margins of a symmetrical inverter (where PMOS and NMOS transistor have equal currentdriving strength) approach VDD/2 The steady-state response is not affected by fanout • Its propagation delay is dominated by the time it takes to charge or discharge the load capacitor CL To a first order, it can be approximated as R eqn + R eqp t p = 0.69C L  -  Keeping the load capacitance small is the most effective means of implementing high-performance circuits Transistor sizing may help to improve performance as long as the delay is dominated by the extrinsic (or load) capacitance of fanout and wiring • The power dissipation is dominated by the dynamic power consumed in charging and discharging the load capacitor It is given by P0→1 CLVDD2f The dissipation is proportional to the activity in the network The dissipation due to the direct-path currents occurring during switching can be limited by careful tailoring of the signal chapter5.fm Page 227 Friday, January 18, 2002 9:01 AM Section 5.8 To Probe Further 227 slopes The static dissipation can usually be ignored but might become a major factor in the future as a result of subthreshold currents • Scaling the technology is an effective means of reducing the area, propagation delay and power consumption of a gate The impact is even more striking if the supply voltage is scaled simultaneously • The interconnect component is gradually taking a larger fraction of the delay and performance budget 5.8 To Probe Further The operation of the CMOS inverter has been the topic of numerous publications and textbooks Virtually every book on digital design devotes a substantial number of pages to the analysis of the basic inverter gate An extensive list of references was presented in Chapter Some references of particular interest that were explicitly quoted in this chapter are given below REFERENCES [Dally98] W Dally and J Poulton, Digital Systems Engineering, Cambridge University Press, 1998 [Fisher98] P D Fisher and R Nesbitt, ``The Test of Time: Clock-Cycle Estimation and Test Challenges for Future Microprocessors,'' IEEE Circuits and Devices Magazine, 14(2), pp 37-44, 1998 [Hedenstierna87] N Hedenstierna and K Jeppson, “CMOS Circuit Speed and Buffer Optimization,” IEEE Transactions on CAD, Vol CAD-6, No 2, pp 270-281, March 1987 [Liu93] D Liu and C Svensson, “Trading speed for low power by choice of supply and threshold voltages”, IEEE Journal of Solid State Circuits, Vol.28, no.1, pp 10-17, Jan 1993, p.10-17 [Mead80] C Mead and L Conway, Introduction to VLSI Systems, Addison-Wesley, 1980 [Sakurai97] T.Sakurai, H.Kawaguchi, T.Kuroda, “Low-Power CMOS Design through VTH Control and Low-Swing Circuits,” Digest International Symp.on Low-Power Electronics and Design, pp.1-6, Sept 1997 Also in T.Sakurai, T.Kuroda, “Low Voltage Technology and Circuits,” Mead Microelectronics Conference, Lausanne, Switzerland, June 1997 [Sedra87] Sedra and Smith, MicroElectronic Circuits, Holt, Rinehart and Winston, 1987 [Swanson72] R Swanson and J Meindl, “Ion-Implanted Complementary CMOS transistors in LowVoltage Circuits,” IEEE Journal of Solid-State Circuits, Vol SC-7, No 2, pp.146-152, April 1972 [Veendrick84] H Veendrick, “Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits,” IEEE Journal of Solid-State Circuits, Vol SC-19, no 4, pp 468–473, 1984 chapter5.fm Page 228 Friday, January 18, 2002 9:01 AM 228 5.9 THE CMOS INVERTER Chapter Exercises and Design Problems For all problems, use the device parameters provided in Chapter (as well as the inside back cover), unless otherwise mentioned DESIGN PROBLEM Using the 1.2 µm CMOS introduced in Chapter 2, design a static CMOS inverter that meets the following requirements: Matched pull-up and pull-down times (i.e., tpHL = tpLH) = nsec (± 0.1 nsec) The load capacitance connected to the output is equal to pF Notice that this capacitance is substantially larger than the internal capacitances of the gate Determine the W and L of the transistors To reduce the parasitics, use minimal lengths (L = 1.2 µm) for all transistors Verify and optimize the design using SPICE after proposing a first design using manual computations Compute also the energy consumed per transition If you have a layout editor (such as MAGIC) available, perform the physical design, extract the real circuit parameters, and compare the simulated results with the ones obtained earlier CHAPTER THE CMOS INVERTER Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design 5.1 Exercises and Design Problems 5.4.2 5.2 The Static CMOS Inverter — An Intuitive Perspective Propagation Delay: First-Order Analysis 5.4.3 Propagation Delay from a Design Perspective 5.3 Evaluating the Robustness of the CMOS Inverter: The Static Behavior Switching Threshold 5.5.1 Dynamic Power Consumption 5.3.2 Noise Margins 5.5.2 Static Consumption Robustness Revisited 5.5.3 Putting It All Together 5.5.4 Analyzing Power Consumption Using SPICE Performance of CMOS Inverter: The Dynamic Behavior 5.4.1 180 Power, Energy, and Energy-Delay 5.3.1 5.3.3 5.4 5.5 Computing the Capacitances 5.6 Perspective: Technology Scaling and its Impact on the Inverter Metrics Section 5.1 181 Exercises and Design Problems [M, SPICE, 3.3.2] The layout of a static CMOS inverter is given in Figure 5.1 (λ = 0.125 µm) a Determine the sizes of the NMOS and PMOS transistors b Plot the VTC (using HSPICE) and derive its parameters (VOH, VOL, VM, VIH, and VIL) c Is the VTC affected when the output of the gates is connected to the inputs of similar gates? GND Poly In VDD = 2.5 V Poly 2λ 5.1 Exercises and Design Problems PMOS NMOS Metal1 Out Metal1 Figure 5.1 CMOS inverter layout d Resize the inverter to achieve a switching threshold of approximately 0.75 V Do not layout the new inverter, use HSPICE for your simulations How are the noise margins affected by this modification? Figure 5.2 shows a piecewise linear approximation for the VTC The transition region is approximated by a straight line with a slope equal to the inverter gain at VM The intersection of this line with the VOH and the VOL lines defines VIH and VIL a The noise margins of a CMOS inverter are highly dependent on the sizing ratio, r = kp/kn, of the NMOS and PMOS transistors Use HSPICE with VTn = |VTp| to determine the value of r that results in equal noise margins? Give a qualitative explanation b Section 5.3.2 of the text uses this piecewise linear approximation to derive simplified expressions for NMH and NML in terms of the inverter gain The derivation of the gain is based on the assumption that both the NMOS and the PMOS devices are velocity saturated at VM For what range of r is this assumption valid? What is the resulting range of VM ? c Derive expressions for the inverter gain at VM for the cases when the sizing ratio is just above and just below the limits of the range where both devices are velocity saturated What are the operating regions of the NMOS and the PMOS for each case? Consider the effect of channel-length modulation by using the following expression for the small-signal resistance in the saturation region: ro,sat = 1/(λID) 182 THE CMOS INVERTER Chapter Vout VOH VM Vin VOL VIL VIH Figure 5.2 A different approach to derive VIL and VIH [M, SPICE, 3.3.2] Figure 5.3 shows an NMOS inverter with resistive load a Qualitatively discuss why this circuit behaves as an inverter b Find VOH and VOL calculate VIH and VIL c Find NML and NMH, and plot the VTC using HSPICE d Compute the average power dissipation for: (i) Vin = V and (ii) Vin = 2.5 V +2.5 V RL = 75 kΩ Vout Vin M1 W/L = 1.5/0.5 Figure 5.3 Resistive-load inverter e Use HSPICE to sketch the VTCs for RL = 37k, 75k, and 150k on a single graph f Comment on the relationship between the critical VTC voltages (i.e., VOL, VOH, VIL, VIH ) and the load resistance, RL g Do high or low impedance loads seem to produce more ideal inverter characteristics? [E, None, 3.3.3] For the inverter of Figure 5.3 and an output load of pF: a Calculate tplh, tphl, and b Are the rising and falling delays equal? Why or why not? c Compute the static and dynamic power dissipation assuming the gate is clocked as fast as possible The next figure shows two implementations of MOS inverters The first inverter uses only NMOS transistors Section 5.1 Exercises and Design Problems 183 a Calculate VOH, VOL, VM for each case VDD = 2.5V V DD = 2.5V M2 M4 W/L=0.75/0.25 W/L=0.375/0.25 VOUT V OUT VIN VIN M3 W/L=0.375/0.25 M1 W/L=0.75/0.25 Figure 5.4 Inverter Implementations b Use HSPICE to obtain the two VTCs You must assume certain values for the source/drain areas and perimeters since there is no layout For our scalable CMOS process, λ = 0.125 µm, and the source/drain extensions are 5λ for the PMOS; for the NMOS the source/drain contact regions are 5λx5λ c Find VIH , VIL, NM L and NMH for each inverter and comment on the results How can you increase the noise margins and reduce the undefined region? d Comment on the differences in the VTCs, robustness and regeneration of each inverter Consider the following NMOS inverter Assume that the bulk terminals of all NMOS device are connected to GND Assume that the input IN has a 0V to 2.5V swing VDD= 2.5V VDD= 2.5V M3 x M2 OUT IN a b c d M1 Set up the equation(s) to compute the voltage on node x Assume γ=0.5 What are the modes of operation of device M2? Assume γ=0 What is the value on the output node OUT for the case when IN =0V?Assume γ=0 Assuming γ=0, derive an expression for the switching threshold (VM) of the inverter Recall that the switching threshold is the point where VIN= VOUT Assume that the device sizes for M1, M2 and M3 are (W/L)1, (W/L)2, and (W/L)3 respectively What are the limits on the switching threshold? For this, consider two cases: i) (W/L)1 >> (W/L)2 184 THE CMOS INVERTER Chapter ii) (W/L)2 >> (W/L)1 Consider the circuit in Figure 5.5 Device M1 is a standard NMOS device Device M2 has all the same properties as M1, except that its device threshold voltage is negative and has a value of -0.4V Assume that all the current equations and inequality equations (to determine the mode of operation) for the depletion device M2 are the same as a regular NMOS Assume that the input IN has a 0V to 2.5V swing VDD= 2.5 V M2 (2µm/1µm), VTn = -0.4V OUT IN M1 (4µm/1µm) Figure 5.5 A depletion load NMOS inverter a Device M2 has its gate terminal connected to its source terminal If VIN = 0V, what is the output voltage? In steady state, what is the mode of operation of device M2 for this input? b Compute the output voltage for VIN = 2.5V You may assume that VOUT is small to simplify your calculation In steady state, what is the mode of operation of device M2 for this input? c Assuming Pr(IN =0)= 0.3, what is the static power dissipation of this circuit? [M, None, 3.3.3] An NMOS transistor is used to charge a large capacitor, as shown in Figure 5.6 a Determine the tpLH of this circuit, assuming an ideal step from to 2.5V at the input node b Assume that a resistor RS of kΩ is used to discharge the capacitance to ground Determine tpHL c Determine how much energy is taken from the supply during the charging of the capacitor How much of this is dissipated in M1 How much is dissipated in the pull-down resistance during discharge? How does this change when RS is reduced to kΩ d The NMOS transistor is replaced by a PMOS device, sized so that kp is equal to the kn of the original NMOS Will the resulting structure be faster? Explain why or why not VDD = 2.5V In 20 M1 Out CL = pF Figure 5.6 Circuit diagram with annotated W/L ratios The circuit in Figure 5.7 is known as the source follower configuration It achieves a DC level shift between the input and the output The value of this shift is determined by the current I0 Assume xd=0, γ=0.4, 2|φf|=0.6V, VT0=0.43V, kn’=115µA/V2 and λ=0 Section 5.1 Exercises and Design Problems 185 VDD = 2.5V VDD = 2.5V Io Vi M1 1um/0.25um Vi M1 1um/0.25um Vo Vo Vbias= 0.55V M2 LD=1um Io (a) (b) Figure 5.7 NMOS source follower configuration 10 a Suppose we want the nominal level shift between Vi and Vo to be 0.6V in the circuit in Figure 5.7 (a) Neglecting the backgate effect, calculate the width of M2 to provide this level shift (Hint: first relate Vi to Vo in terms of Io) b Now assume that an ideal current source replaces M2 (Figure 5.7 (b)) The NMOS transistor M1 experiences a shift in VT due to the backgate effect Find VT as a function of Vo for Vo ranging from to 2.5V with 0.5V intervals Plot VT vs Vo c Plot Vo vs Vi as Vo varies from to 2.5V with 0.5 V intervals Plot two curves: one neglecting the body effect and one accounting for it How does the body effect influence the operation of the level converter? d At Vo(with body effect) = 2.5V, find Vo(ideal) and thus determine the maximum error introduced by the body effect For this problem assume: VDD = 2.5V, W P/L = 1.25/0.25, WN/L = 0.375/0.25, L=Leff =0.25µm (i.e xd= 0µm), CL=Cinv2 -1 gate, kn’ = 115µA/V , kp’= -30µA/V , Vtn0 = | Vtp0 | = 0.4V, λ = 0V , γ = 0.4, 2|φf|=0.6V, and tox = 58A Use the HSPICE model parameters for parasitic capacitance given below (i.e Cgd0, Cj, Cjsw), and assume that VSB=0V for all problems except part (e) 186 THE CMOS INVERTER Chapter VDD = 2.5V L = LP = LN = 0.25µm VOUT VIN CL = Cinv-gate (Wp/Wn = 1.25/0.375) + VSB Figure 5.8 CMOS inverter with capacitive 11 ## Parasitic Capacitance Parameters (F/m)## NMOS: CGDO=3.11x10-10, CGSO=3.11x10-10, CJ=2.02x10-3, CJSW=2.75x10-10 PMOS: CGDO=2.68x10-10, CGSO=2.68x10-10, CJ=1.93x10-3, CJSW=2.23x10-10 a What is the Vm for this inverter? b What is the effective load capacitance CLeff of this inverter? (include parasitic capacitance, refer to the text for Keq and m.) Hint: You must assume certain values for the source/drain areas and perimeters since there is no layout For our scalable CMOS process, λ = 0.125 µm, and the source/drain extensions are 5λ for the PMOS; for the NMOS the source/drain contact regions are 5λx5λ c Calculate tPHL, tPLH assuming the result of (b) is ‘CLeff = 6.5fF’ (Assume an ideal step input, i.e trise=tfall=0 Do this part by computing the average current used to charge/discharge CLeff.) d Find (Wp/Wn) such that tPHL = tPLH e Suppose we increase the width of the transistors to reduce the tPHL, tPLH Do we get a proportional decrease in the delay times? Justify your answer f Suppose VSB = 1V, what is the value of Vtn, Vtp, Vm? How does this qualitatively affect CLeff? Using Hspice answer the following questions a Simulate the circuit in Problem 10 and measure tP and the average power for input Vin: pulse(0 VDD 5n 0.1n 0.1n 9n 20n), as VDD varies from 1V - 2.5V with a 0.25V interval [tP = (tPHL + tPLH ) / 2] Using this data, plot ‘tP vs VDD’, and ‘Power vs VDD’ Specify AS, AD, PS, PD in your spice deck, and manually add CL = 6.5fF Set VSB = 0V for this problem b For Vdd equal to 2.5V determine the maximum fan-out of identical inverters this gate can drive before its delay becomes larger than ns c Simulate the same circuit for a set of ‘pulse’ inputs with rise and fall times of tin_rise,fall =1ns, 2ns, 5ns, 10ns, 20ns For each input, measure (1) the rise and fall times tout_rise and Section 5.1 12 Exercises and Design Problems 187 tout_fall of the inverter output, (2) the total energy lost Etotal, and (3) the energy lost due to short circuit current Eshort Using this data, prepare a plot of (1) (tout_rise+tout_fall)/2 vs tin_rise,fall, (2) Etotal vs tin_rise,fall, (3) Eshort vs tin_rise,fall and (4) Eshort/Etotal vs tin_rise,fall d Provide simple explanations for: (i) Why the slope for (1) is less than 1? (ii) Why Eshort increases with tin_rise,fall? (iii) Why Etotal increases with tin_rise,fall? Consider the low swing driver of Figure 5.9: VDD = 2.5 V W = 1.5 µm L n 0.25 µm W µm = L p 0.25 µm Vin Vout 2.5V CL=100fF 0V Figure 5.9 Low Swing Driver 13 a What is the voltage swing on the output node (Vout)? Assume γ=0 b Estimate (i) the energy drawn from the supply and (ii) energy dissipated for a 0V to 2.5V transition at the input Assume that the rise and fall times at the input are Repeat the analysis for a 2.5V to 0V transition at the input c Compute tpLH (i.e the time to transition from VOL to (VOH + VOL) /2) Assume the input rise time to be VOL is the output voltage with the input at 0V and VOH is the output voltage with the input at 2.5V d Compute VOH taking into account body effect Assume γ = 0.5V1/2 for both NMOS and PMOS Consider the following low swing driver consisting of NMOS devices M1 and M2 Assume an NWELL implementation Assume that the inputs IN and IN have a 0V to 2.5V swing and that VIN = 0V when VIN = 2.5V and vice-versa Also assume that there is no skew between IN and IN (i.e., the inverter delay to derive IN from IN is zero) VLOW= 0.5V IN 25µm/0.25µm M2 Out IN M1 25µm/0.25µm CL=1pF Figure 5.10 Low Swing Driver a What voltage is the bulk terminal of M2 connected to? 188 THE CMOS INVERTER Chapter b What is the voltage swing on the output node as the inputs swing from 0V to 2.5V Show the low value and the high value c Assume that the inputs IN and IN have zero rise and fall times Assume a zero skew between IN and IN Determine the low to high propagation delay for charging the output node measured from the the 50% point of the input to the 50% point of the output Assume that the total load capacitance is 1pF, including the transistor parasitics d Assume that, instead of the 1pF load, the low swing driver drives a non-linear capacitor, whose capacitance vs voltage is plotted below Compute the energy drawn from the low supply for charging up the load capacitor Ignore the parasitic capacitance of the driver circuit itself 5V 1V 1.5V 2V 2.5V 3V 14 Voltage, V The inverter below operates with VDD=0.4V and is composed of |V t| = 0.5V devices The devices have identical I0 and n a Calculate the switching threshold (VM) of this inverter b Calculate VIL and VIH of the inverter VDD = 0.4V VIN VOUT Figure 5.11 Inverter in Weak Inversion Regime 15 Sizing a chain of inverters a In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with input capacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown in Figure 5.12 Assume that the propagation delay of a minimum size inverter is 70 ps Also assume Section 5.1 Exercises and Design Problems 189 that the input capacitance of a gate is proportional to its size Determine the sizing of the two additional buffer stages that will minimize the propagation delay ‘1’ is the minimum size inverter In OUT ? ? Ci = 10fF CL = 20pF Added Buffer Stage Figure 5.12 Buffer insertion for driving large loads 16 b If you could add any number of stages to achieve the minimum delay, how many stages would you insert? What is the propagation delay in this case? c Describe the advantages and disadvantages of the methods shown in (a) and (b) d Determine a closed form expression for the power consumption in the circuit Consider only gate capacitances in your analysis What is the power consumption for a supply voltage of 2.5V and an activity factor of 1? [M, None, 3.3.5] Consider scaling a CMOS technology by S > In order to maintain compatibility with existing system components, you decide to use constant voltage scaling a In traditional constant voltage scaling, transistor widths scale inversely with S, W∝1/S To avoid the power increases associated with constant voltage scaling, however, you decide to change the scaling factor for W What should this new scaling factor be to maintain approximately constant power Assume long-channel devices (i.e., neglect velocity saturation) b How does delay scale under this new methodology? c Assuming short-channel devices (i.e., velocity saturation), how would transistor widths have to scale to maintain the constant power requirement? 190 THE CMOS INVERTER DESIGN PROBLEM Using the 0.25 µm CMOS introduced in Chapter 2, design a static CMOS inverter that meets the following requirements: Matched pull-up and pull-down times (i.e., tpHL = tpLH) = nsec (± 0.1 nsec) The load capacitance connected to the output is equal to pF Notice that this capacitance is substantially larger than the internal capacitances of the gate Determine the W and L of the transistors To reduce the parasitics, use minimal lengths (L = 0.25 µm) for all transistors Verify and optimize the design using SPICE after proposing a first design using manual computations Compute also the energy consumed per transition If you have a layout editor (such as MAGIC) available, perform the physical design, extract the real circuit parameters, and compare the simulated results with the ones obtained earlier Chapter ... success of a component 10 0000000 Pentium Pentium III Pentium II Transistors 10 000000 Pentium ® 10 00000 486 386 10 0000 286 ™ 8086 10 000 4004 10 00 19 70 8080 8008 19 75 19 80 19 85 19 90 19 95 2000 Year of... bits per chip 10 8 256 Mbits 10 7 64 Mbits 10 6 Book Book 16 Mbits Mbits 10 5 Mbits 10 4 256 Kbits 0 .15 µm 0 .15 -0.2µm 0.25-0.3µm 0.35-0.4µm 0.5-0.6µm 0.7-0.8µm 1. 0 -1. 2µm 1. 6-2.4µm 64 Kbits Encyclopedia... Difference Engine I (part of which is shown in Figure 1. 1) required 25,000 mechanical parts at a total cost of 17 ,470 (in 18 34!) Figure 1. 1 Working part of Babbage’s Difference Engine I (18 32), the first
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