ADVANCED SOURCE/DRAIN CONTACT ENGINEERING FOR LOW PARASITIC SERIES RESISTANCE KOH TIAN YI, ALVIN NATIONAL UNIVERSITY OF SINGAPORE 2008 ADVANCED SOURCE AND DRAIN CONTACT ENGINEERING FOR LOW PARASITIC SERIES RESISTANCE KOH TIAN YI, ALVIN (B.ENG. (HONS.), NUS) A THESIS SUBMITTED FOR THE DEGREE OF MASTER ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2008 Acknowledgements I would like to express my gratitude to my main supervisor, Dr Yee-Chia Yeo. He has given me invaluable advice and guidance over the past years of my M.Eng candidature. I would like to thank him for his patience. He has always been very encouraging and supportive of my work. He is always approachable and it is during the many discussions with him that ideas flow and problems are seen from an interesting perspective. Next, special thanks goes to my co-supervisor Dr Patrick Lo and former cosupervisor Dr Balasubramanian for their help during my stay in A*Star Institute of Microelectronic (IME). They provided me with the necessary means to perform all my device fabrication and characterization. I would also like to acknowledge Chartered Semiconductor Manufacturing for funding my graduate research study. Special thanks to Dr Lap Chan and Dr Ng Chee Mang for their teaching and guidance. Their rich industry experience has enriched my graduate study. My work in A*Star SIMTech was made possible with the help from Dr Wang Xincai. He is very supportive and approachable, which allow my work in SIMTech to be completed promptly. i I would also like to thank the members in my research group, especially Rinus. He has been a supportive and wonderful friend. Without his resources and discussions with him, many experiments in this work would not have been possible. Through working with him on the various conference submissions, I am able to tap onto his years of experience working on silicides and accelerate my learning. I would also like to thank my other group members, Hock Chun, Lina, Fangyue, Andy, Kian Ming, Shao Ming and Hoong Shing, for giving me such a wonderful memory and experience during my stay in Silicon Nano Device Laboratory (SNDL). I will miss the interesting conversations and hilarious jokes we had during our meal time and tea-break sessions. Special thanks goes out to all the staff and graduate students from SNDL who has helped me in one way or another. Lastly, I would like to give a big thank you to my parents and brother who has been very supportive and understanding throughout the course of my research. This has been indeed the most wonderful experience! Thank you everyone! ii Table of Contents Acknowledgements i Table of Contents iii Abstract vi List of Tables viii List of Figures ix Introduction 1.1 Background 1.2 Parasitic Series Resistance RPSR 1.2.1 S/D Resistance RSD and S/D Extension Resistance RSDE 1.2.2 Silicide-S/D Contact Resistance RCON 1.3 Objective of the Research 1.4 Outline of the Report 1.5 References Nickel-Aluminum Alloy Silicides for Contact Resistance Reduction 10 17 2.1 Introduction 17 2.2 Electron Barrier Height Reduction using Nickel Aluminide Disilicide 18 2.2.1 Sample Fabrication 18 2.2.2 Material Characterization 19 2.2.3 Device Fabrication 32 2.2.4 Device Characterization 34 2.2.5 Summary 35 2.3 Reference 37 iii Impurity Engineering in NiSi and Pure Rare Earth Silicide for Contact Resistance Lowering 3.1 40 Contact Resistance Tuning in MuGFETs with Nickel Silicide:Carbon Using a Dysprosium Interlayer 41 3.1.1 Introduction 41 3.1.2 Sample Fabrication 42 3.1.3 Material Characterization 42 3.1.4 Device Fabrication 49 3.1.5 Device Characterization 51 3.1.6 Summary 53 3.2 Formation of Pure YSi2 for Contact Resistance Reduction 54 3.2.1 Sample Fabrication 54 3.2.2 Material Characterization 55 3.2.3 Summary 58 3.3 Reference 59 Integration of Pulse Laser Annealing on Silicon-Carbon Source/Drain in MuGFETs 63 4.1 Introduction 63 4.2 Study of Pulse Laser Annealing on Si1-yCy S/D in MuGFETs 65 4.2.1 Device Fabrication 65 4.2.2 Pulse Laser Annealing for Enhanced Dopant Activation 67 4.2.3 Pulse Laser Annealing for High Carbon Substitutionality 69 4.2.4 Device Characterization 71 4.3 Summary 77 4.4 Reference 79 Conclusion and Future Work 5.1 Conclusion 83 83 iv 5.1.1 Nickel-Aluminum Alloy Silicides for Contact Resistance Reduction 5.1.2 Impurity Engineering in NiSi and Pure Rare Earth Silicide for Contact Resistance Lowering 5.1.3 84 Integration of Pulse Laser Annealing on Silicon-Carbon Source/Drain in MuGFETs 5.2 83 84 Future Work 85 Appendix A: Publication List 86 v Advanced Source/Drain Contact Engineering For Low Parasitic Series Resistance Abstract Complementary Metal-Oxide-Semiconductor (CMOS) scaling and the application of strain have led to the increasing dominance of parasitic source/drain (S/D) series resistance. This is expected to limit device performance in the 32 nm technology node and beyond. In this work, novel silicide processes and materials were evaluated as potential solutions to address the parasitic series resistance issue. Nickel-aluminum alloy film (Ni1-xAlx) was proposed as an alternative silicide material. Investigations have shown that the electron Schottky-Barrier (ФBn) can be effectively tuned for contact resistance reduction. Process was optimized to avoid film agglomeration when films with aluminum content as high as 51 % were used. This gives a minimum ФBn of 400 meV. The compatibility of the silicide for current devices was experimentally verified when the silicide was integrated into n-channel transistors. Evaluation of the electrical performance of the devices show that drive current enhancement can indeed be achieved. A novel approach of using dysprosium (Dy) as an interlayer between nickel (Ni) and silicon-carbon (Si1-yCy) during the silicidation process was investigated. A 2.5 nm thick Dy-based interlayer has been shown to exist at nickel-dysprosium-silicide (Ni[Dy]Si:C) and the Si1-yCy interface. The low ФBn of 280 meV was attributed to the interfacial dipole mechanism. Carbon re-distribution in the film after silicidation process vi and the associated enhanced thermal stability of the film was also studied. Integration of Ni[Dy]Si:C on Multiple-Gate Field-Effect-Transistors (MuGFETs) has resulted in dramatic performance enhancement, validating the importance of impurity engineering for contact resistance lowering. In addition, a technique for yttrium silicide (YSi2) deposition was devised to minimize the oxidizing issue and a low ФBn of 170 meV was reported. Laser annealing for dopant activation has been widely reported. However, there have not been many reports on the application of laser on strained devices. This is addressed with the investigation of pulse laser annealing (PLA) on Si1-yCy MuGFETs. PLA was not only observed to alleviate the problem of dopant deactivation in strain S/D, it increases the substitutional carbon concentration. The significant performance improvement in the saturation drain current (IDsat) is attributed to the improved strain and the reduction in the various components of the parasitic series resistance. vii List of Tables Table 2.1 Table illustrates the sputtering power of Ni and Al targets and the resulting Al atomic concentration in the deposited film. ---------------------------------------- 20 Table 3.1 Elements selected for ФBn tuning and their respective work function value. - 41 viii The IDsat is measured at a gate overdrive of 1.2 V with a VDS of 1.2 V. IDsat is then plotted as a function of gate length, as shown in Figure 4.11. Comparing MuGFETs annealed using RTA and PLA, we observe an average of ~53 % increase in the IDsat. It is commonly known that the slope of the Rtot-LG plot is inversely proportionate to the carrier’s mobility [4.17]. However, in Figure 4.10 (a), covers a large range of LG up to 1150 nm, with large incremental LG steps. As mobility enhancement due to S/D stressors is not expected at large gate lengths, a difference in the slope is not generally expected. In addition, mobility in locally-strained transistors should be extracted from data covering a small range of LG with fine LG steps for accurate results. However, this is not available in this work. An alternative method to distinguish the contributions of enhanced strain effects and series resistance to drive current improvement has to be sought. Drain Current IDsat (µA/µm) 200 MuGFETs using RTA 160 MuGFETs using PLA ~60% 120 80 ~45% 40 0.2 0.4 0.6 0.8 1.0 1.2 Gate Length L G (µ m) Figure 4.11 Plot of IDsat as a function of LG. On the average, IDsat enhancement is ~53%. IDsat enhancement is observed to increase with device scaling, providing evidence for improved strained effect with the use of PLA. 76 For a given applied VGS, a transistor with a higher RPSR has a lower intrinsic gate voltage V’GS due to the voltage drop across the source side series resistance RPSR/2, where V’GS = VGS-IDRPSR/2. To eliminate the effect of this on the saturation drain current, a compensated V’GS (where V’GS = VGS-IDRPSR/2) of 1.2 V, which excludes the potential drop due to the source side resistance is therefore used to compare the drain current [4.18]. From the above analysis it is observed that the RPSR-independent drive current of the laser-annealed device in Figure 4.9 is still 15% higher than that of the device which went through RTA. This value may not be absolute; nonetheless, the devices qualitatively demonstrated that the higher Idsat must be due to effects other than series resistance, which is improved strain in this case. This is consistent with enhanced strain effects due to the increased Csub. Higher IDsat improvement is observed for smaller LG, demonstrating the benefits of the enhanced strain effect in short channel laser annealed MuGFETs. This evidently shows that PLA is a promising tool for realizing low parasitic series resistance and achieving higher drive current in advanced CMOS devices. 4.3 Summary In this work, it is demonstrated for the first time, that the use of PLA in epitaxial Si1-yCy S/D, similar to Si S/D, enhances the dopant activation. Resistivity of Si1-yCy S/D is reduced by as much as ~60 %. A further attractiveness of the PLA is that it promotes carbon atoms occupying substitional sites, leading to improved strain. Epitaxially grown Si0.99C0.01 S/D annealed at a laser fluence of 250 mJ/cm2 with 10 irradiation has 1.21 % Csub compared to rapid thermally annealed S/D’s 0.71 %. This translates to a strain improvement of up to 0.22 %. These verification and subsequent process integration 77 attests the compatibility of PLA on Si1-yCy S/D. This work also demonstrates the feasibility of overcoming process complexities associated with laser annealing of threedimensional device architectures through engineering the surface reflectance of gate stack and S/D regions with a SiO2 optical layer. This is easily compatible to the presently used process flow and minimizes the number of additional steps. Comparison of RTA and PLA on MuGFETs shows a substantial improvement of 53 % in the IDsat which can be attributed mainly to the enhanced strain and lower series resistance effects. By extrapolating to high VGS, RPSR can be extracted for the devices. It is shown that RPSR can be significantly reduced by as much as 63 % when PLA is applied to the MuGFET. To decouple enhancement brought about by strain and RPSR reduction, a compensated VGS, which is independent of RPSR effect is used for analysis. MuGFETs undergone PLA is reported to have a 15 % enhancement in drive current over rapid thermally annealed MuGFETs. In addition, it is demonstrated that further scaling of the MuGFETs leads to higher IDsat improvement. Hence, this work provides a framework for the integration of pulsed laser annealing process to fabricate MuGFETs with Si1-yCy S/D stressors and also highlights PLA’s attraction for application in advanced CMOS devices. 78 4.4 References [4.1] Y. -C. Liu, O. Gluschenkov, J. -H. Li, A. Madan, A. Ozcan, B. Kim, T. Dyer, A. Chakravarti, K. Chan, C. Lavoie, I. Popova, T. Pinto, N. Rovedo, Z. Luo, R. Loesing, W. Henson, and K. Rim, “Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy,” in Symposium VLSI Technology Digest, 2007, pp. 44-45. [4.2] P. Grudowski, V. Dhandapani, S. Zollnew, D. Goedeke, K. Loiko, D. Tekleab, V. Adams, G. Spencer, H. Desjardins, L. Prabhu, R. Garcia, M. Foisy, D. Theodore, M. Bauer, D. Weeks, S. Thomas, A. Thean, and B. White, “An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing,” in IEEE International SOI Conference Proceedings, 2007, pp.17-18. [4.3] A. R. Bean, and R. C. Newman, “The Effect of Carbon on Thermal Donor Formation in Heat Treated Pulled Silicon Crystals,” Journal of Physics and Chemistry of Solids, vol. 33, no. 2, pp. 255 – 268, Jun. 1971. [4.4] T. Nozaki, Y. Yatsurugi, and N. Akiyama, “Concentration and Behhavior of Carbon in Semiconductor Silicon,” Journal of Electrochemical Society, vol. 117, pp. 2053-2055, 1970. [4.5] K. -J. Chui, K. -W. Ang, N. Balasubramanian, M. -F. Li, G. Samudra, and Y. -C. Yeo, "N-MOSFET with Silicon-carbon Source/Drain for Enhancement of Carrier Transport," IEEE Transaction on Electron Devices, vol. 54, no. 2, pp. 249-256, Feb. 2007. 79 [4.6] A. C. Mocuta, and D. W. Greve, “The Role of Surface and Gas Phase Reactions,” Journal of Applied Physics, vol. 85, no. 2, pp. 1240 – 1242, Jan. 1999. [4.7] J. C. Baker and J. W. Cahn, “Solute Trapping by Rapid Solidification,” Acta Metall., vol. 17 no. 5, pp. 575-578, May 1969. [4.8] S. U. Campisano, G. Foti, P. Baeri, M. G. Grimaldi and E. Rimini, “Solute Trapping by Moving Interface in Ion-implanted Silicon,” Applied Physics Letters, vol. 37 no. 8, pp. 719-722, Oct. 1980. [4.9] G. Fortunato, L. Mariucci, A. L. Magna, P. Alippi, M. Italia, V. Privitera, B. Svensson, and E. Monakhov, “Electrical Activation Phenomena Induced by Excimer Laser Annealing in B-implanted Silicon,” Applied Physics Letters, vol. 85 no. 12, pp. 2268-2270, Sept. 2004. [4.10] C. Park, S. -D. Kim, Y. Wang, S. Talwar, and J. C. S. Woo, “50 nm SOI CMOS Transistors with Ultra Shallow Junction Using Laser Annealing and PreAmorphization Implantation,” in Symposium on VLSI Technology Digest, 2001, pp. 69-70. [4.11] Y. Setiawan, P. S. Lee, K. L. Pey, X. C. Wang, G. C. Lim, and F. L. Chow, “Nickel Silicide Formation Using Multiple-Pulsed Laser Annealing,” Journal of Applied Physics, vol. 101, no. 3, pp. 1063-1067, Feb. 2007. [4.12] H. Tsukamoto, H. Yamamoto, T. Noguchi, and T. Suzuki, “Selective Annealing Utilizing Single Pulse Excimer Laser Irradiation for Short Channel Metal-OxideSemiconductor Field-Effect Transistors,” Japanese Journal of Applied Physics, vol. 32, pp. 967-970, Jul. 1993. 80 [4.13] M. Hernansez, J. Venturini, D. Berard, G. Kerrien, T. Sarnet, D. Debarre, J. Boulmer, C. Laviron, D. Camel, J. -L. Santailler, and H. Akhouayri, “Laser Thermal Processing Using an Optical Coating for Ultra Shallow Junction Formation,” Materials Science and Engineering B, vol. 114-115, pp. 105-108, Jul. 2004. [4.14] R. T. -P. Lee, A. T. -Y. Koh, W. -W. Fang, K. -M. Tan, A. E. -J. Lim, T. -Y. Liow, S. -Y. Chow, A. M. Yong, H. S. Wong, G. -Q. Lo, G. S. Samudra, D. -Z. Chi, and Y. -C. Yeo, “Novel and Cost-Efficient Single Metallic Silicide Integration Solution with Dual Schottky-Barrier Achieved by Aluminum Inter-diffusion for FinFET CMOS Technology with Enhanced Performance,” in Symposium VLSI Technology Digest, 2008, pp. 28 – 29. [4.15] D. Esseni, H. Iwai, M. Saito, and B. Ricco, “Nonscaling of MOSFET’s Linear Resistance in the Deep Submicrometer Regime,” IEEE Electron Device Letters, vol. 19, no. 4, pp. 131-133, Apr. 1998. [4.16] P. Verheyen, N. Collaert, R. Rooyackers, R. Loo, D. Shamiryan, A. De Keersgieter, G. Eneman, F. Leys, A. Dixit., M. Goodwin, Y. S. Yim, M. Caymax, K. De Meyer, P. Absil, M. Jurczak, S. Biesmans, “25% Drive Current Improvement for p-type Mulitple Gate FET (MuGFET) Devices by the Introduction of Recessed Si0.8Ge0.2 in the Source and Drain Regions,” in Symposium VLSI Technology Digest, 2005, pp. 194 – 195. [4.17] G. Niu, J. D. Cressler, S. J. Mathew, and S. Subbanna, “ A Total Resistance Slope-Based Effective Channel Mobility Extraction Method for Deep 81 Submicrometer CMOS Technology,” IEEE Transactions On Electron Device, vol. 46, no. 9, pp.1912-1914, Sep. 1999. [4.18] K. -W. Ang, K. -J. Chui, A. Madan, L. -Y. Wong, C. -H. Tung, N. Balasubramanian, M. -F. Li, G. S. Samudra, and Y. -C. Yeo, “Strained Thin-Body p-MOSFET With Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance,” IEEE Electron Device Letters, vol. 28, no. 6, pp. 509 – 512, Jun. 2007. 82 Chapter 5 Conclusion and Future Work 5.1 Conclusion Continual scaling of CMOS devices has met with immense challenges. The dominance of RPSR has resulted in diminished gain from scaling and other enhancement techniques. In view of this issue, this thesis has experimentally examined different approaches to alleviate the RPSR problem. 5.1.1 Nickel-Aluminum Alloy Silicides for Contact Resistance Reduction An alternative silicide material is proposed. Using Ni1-xAlx film with different Al concentration, the amount of ФBn modification can be quantified. However, the incorporation of high Al in the film degrades the film quality. To overcome this, the annealing process is carefully studied. With the optimization of the annealing conditions, film with Al concentration as high as 51 %, can be employed for the silicidation process This yielded a 38 % reduction in ФBn. 18 % IDsat enhancement was observed when fabricated N-MOSFETs employ the new silicide material. 83 5.1.2 Impurity Engineering in NiSi and Pure Rare Earth Silicide for Contact Resistance Lowering Various materials were studied as the potential candidate for the interlayer between Ni and Si. Dy yielded the lowest ФBn of 280 meV. This can be attributed to the presence of a DyIL at the Ni[Dy]Si:C/Si0.99C0.01 interface. The physical origin of the reduction is elucidated with the interfacial dipole concepts. Thermal stability of the film is attributed to the presence of 0.8 % atomic concentration of carbon in the silicide. When this silicidation is applied onto MuGFETs, a ~ 41 % IDsat enhancement was observed. Analysis shows that the improved device performance is due to the reduction in the RPSR. Successful demonstration of Ni[Dy]Si:C on MuGFETs for RPSR engineering, illustrates that Ni[Dy]Si:C is a promising silicide material for future device performance enhancement. Challenges in forming YSi2 are resolved by the application of reactive sputtering and HfN capping. The ФBn between YSi2 and n-Si is the lowest reported for any pure rare-earth silicide to date. This makes YSi2 an attractive silicide candidate for advance CMOS devices. 5.1.3 Integration of Pulse Laser Annealing on Silicon-Carbon Source/Drain in MuGFETs The application of PLA on strained Si1-yCy S/D has demonstrated superior dopant and carbon activation compared to RTA. Challenges with the deformation of the gate 84 stack due to excessive thermal stress can be rectified by the use of a SiO2 optical layer to maximize the surface reflectance on the gate stack. The 53 % IDsat improvement from laser annealed MuGFETs can be attributed to the reduced RSD and RSDE due to the enhanced dopant activation, increased in the Csub, reducing RCON and enhances channel strain. In this chapter, PLA has been highlighted to be a promising annealing technique for coming technology nodes. 5.2 Future Work This thesis has opened up several areas which deserve further investigation. These include: • Employing other rare-earth elements for interlayer study. • Investigation of YSi2 for dopant segregation SSDT application. • Reliability issues of laser annealed Si1-yCy S/D. • Alternative optical layer or annealing methodology for more selective annealing to achieve laser annealed MuGFETs with smaller LG. • Efficiency study of PLA on Si1-yCy S/D with higher carbon concentration. • PLA on devices with high-k and metal gate. 85 Appendix A: Publication List [1] R. T. -P. Lee, A. T. -Y. Koh, F. -Y. Liu, W. -W. Fang, T. -Y. Liow, K. -M. Tan, P. -C. Lim, A. E. -J. Lim, M. Zhu, K. -M. Hoe, C. -H. Tung, G. -Q. Lo, X. Wang, G. S. Samudra, D. -Z. Chi, and Y. -C. Yeo, "Route to Low Parasitic Resistance in MuGFETs with Silicon-Carbon Source/Drain: Integration of Novel Low Barrier Ni(M)Si:C Metal Silicides and Pulsed Laser Annealing," IEEE International Electron Device Meeting, 2007, pp. 685-688. [2] A. T. -Y. Koh, R. T. -P. Lee, A. E. -J. Lim, D. M. -Y. Lai, D. -Z. Chi, K. -M. Hoe, N. Balasubramanian, G. S. Samudra, and Y. -C. Yeo, "Nickel-Aluminum Alloy Silicides with High Aluminum Content For Contact Resistance Reduction and Integration in N-Channel Field-Effect Transistors," Journal of Electrochemical Society, vol. 155, no. 3, pp. 151-155, Mar. 2008. [3] A. T. -Y. Koh, R. T. -P. Lee, F. -Y. Liu, T. -Y. Liow, K. -M. Tan, X. Wang, G. S. Samudra, D. -Z. Chi, N. Balasubramanian, and Y. -C. Yeo, "Pulsed Laser Annealing of Silicon-Carbon Source/Drain in Multiple-Gate Transistors for Enhanced Dopant Activation and High Substitutional Carbon Concentration," IEEE Electron Device Letters, vol. 29, no. 5, pp. 454-467, May 2008. [4] R. T. -P. Lee, A. T. -Y. Koh, W. -W. Fang, K. -M. Tan, A. E. -J. Lim, T. -Y. Liow, S. -Y. Chow, A. M. Yong, H. -S. Wong, G. -Q. Lo, G. S. Samudra, D. -Z. 86 Chi, and Y. -C. Yeo, "Novel and Cost-Efficient Single Metallic Silicide Integration Solution with Dual Schottky-Barrier Achieved by Aluminum InterDiffusion for FinFET CMOS Technology with Enhanced Performance," Symposium on VLSI Technology, 2008, pp. 28-29. Collaborative Work [1] E. -J. Lim, R. T.P. Lee, A. T. Y. Koh, G. S. Samudra, D. -L. Kwong, and Y. -C. Yeo, "Effectiveness of aluminum incorporation in nickel silicide and nickel germanide metal gates for work function reduction," in International Conference on Solid State Devices and Materials, 2007. [2] R. T. P. Lee, K. M. Tan, A. E. J. Lim, T. Y. Liow, X. C. Chen, M. Zhu, A. T. Y. Koh, K. M. Hoe, S. Y. Chow, G. Q. Lo, G. S. Samudra, D. Z. Chi, Y. -C. Yeo, "Contact technology employing nickel-platinum germanosilicide alloys for pchannel FinFETs with silicon-germanium source and drain stressors," in International Conference on Solid State Devices and Materials, 2007. [3] R. T. P. Lee, T. -Y. Liow, K. -M. Tan, A. E. -J. Lim, A. T. -Y. Koh, G. -Q. Lo, G. S. Samudra, D. Z. Chi, and Y. -C. Yeo, "Achieving conduction band-edge Schottky barrier height for arsenic-segregated nickel aluminide disilicide and implementation in FinFETs with ultra narrow fin widths," IEEE Electron Device Letters, vol. 29, no. 4, Apr. 2008. 87 [4] H. -S. Wong, A. T. -Y. Koh, H. -C. Chin, R. T. -P. Lee, L. Chan, G. Samudra, and Y. -C. Yeo, "A new salicidation process with Solid Antimony (Sb) Segregation (SSbS) for achieving sub-0.1 eV effective Schottky barrier height and parasitic series resistance reduction in n-channel transistors," in International Symposium on VLSI Technology, Systems and Applications, 2008. [5] H. -S. Wong, F. -Y. Liu, K. -W. Ang, S. -M. Koh, A. T. -Y. Koh, T. -Y. Liow, R. T. -P. Lee, A. E. -J. Lim, W. -W. Fang, M. Zhu, L. Chan, N. Balasubramaniam, G. Samudra, and Y. -C. Yeo, "Selenium co-implantation and segregation as a new contact technology for nanoscale SOI N-FETs featuring NiSi:C formed on silicon-carbon (Si:C) source/drain stressors," in Symposium on VLSI Technology 2008. [6] E. -J. Lim, R. T. P. Lee, A. T. Y. Koh, G. S. Samudra, D. -L. Kwong, and Y. -C. Yeo, "Effectiveness of aluminum incorporation in nickel silicide and nickel germanide metal gates for work function reduction," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 4723-4726, 2008. [7] H. -S. Wong, A. T. -Y. Koh, H. -C. Chin, L. Chan, G. Samudra, and Y. -C. Yeo, "Source and drain series resistance reduction for n-channel transistors using solid Antimony (Sb) segregation (SSbS) during silicidation," IEEE Electron Device Letters, vol. 29, no. 7, pp. 756-758, Jul. 2008. 88 [8] P. S. -Y. Lim, R. T. -P. Lee, A. E. -J. Lim, A. T. -Y. Koh, M. Sinha, D. -Z. Chi, and Y. -C. Yeo, "Schottky-barrier height tuning of nickel silicide on epitaxial silicon-carbon films with high substitutional carbon content," in International Conference on Solid-State Devices and Materials, 2008. 89 Appendix B: Laser Anneal System Setup & Procedure The laser annealing system use in this experiment employs KrF gas as the 248 nm laser source. The shutter is opened and the laser passed through a filter before reflecting on a mirror. The reflected laser beam is then directed to the sample, which is constantly purged with nitrogen gas. To increase the throughput of the system, the stage is controlled by a computer system, which uses G-code computerized numerical control (CNC) software to precisely control the stage movement. Also, knowing the focal length of the laser beam, we can vary the stage height using G-code programming to obtain the required laser energy. Figure B.1 shows the schematic of the laser system. KrF Laser System Mirror Shutter Filter Sample Condenser Lens Sample Holder Computer Control System Computer Controlled Stage Figure B.1 Schematic illustrating the components in the laser annealing system. The system is set to constant high voltage mode between 13 – 18.5 kV. This will correspond to a laser fluence in the system. To determine the final intensity at the sample, 90 the system has to be first calibrated using photo-detector. The fluence at various stage heights and attenuation are then quantified. To setup the stage, refer to Table B.1. G-Code Command Remark x, y stage control. z, u filter setting. 1. Enable x, y, z, u on 'Board 1' 2. Return the stage to default position ho x y z u 3. Set to centre position g90 g1 f1000 x100 y100 g90 absolute position, f300 movement speed z, u stage height and attentuation respectively 4. Enable z, u on 'Board 2' 5. Set to default position ho z u 6. Set the stage height and attenuation g90 g1 f30 z-0.6 u0.2 7. Return to 'Board 1' and set the frequency psop, 1, 0, 5, a z is to compensate sample thickness Frequency, f = + a 10000 8. Pulsing psof, 2, b b = number of pulses 9. Move relative to present location g91 f100 x3 y3 g91 relative position Table B.1 List of steps and respective command to setup the stage for laser annealing. As the intensity of a single pulse laser is not an ideal homogenous step profile (see Figure B.2), cross-stitching annealing methodology with 50 % overlap is adopted to ensure each area is sufficiently annealed. To fully automate the system, a series of Gcodes can be written and loaded into the system when annealing begins. Figure B.2 Cross-stitching annealing to minimize the effect of edge profile. 91 [...]... performance will be limited Figure 1.1 RCH and RPSR converge with technology scaling and RPSR is expected to dominate from 32 nm technology node and beyond Therefore, there is an urgent need for solutions to minimize RPSR [1.3] 1.2 Parasitic Series Resistance RPSR RPSR consists mainly of three elements: the S/D extension (SDE) resistance, RSDE, deep S/D resistance, RSD and the silicide-S/D contact resistance, ... Resistance for Enhanced Performance of Dopant-segregated Source/ Drain MuGFETs,” in Symposium VLSI Technology Digest, 2007, pp 108-109 16 Chapter 2 2 Nickel-Aluminum Alloy Silicides for Contact Resistance Reduction 2.1 Introduction Strain and continual scaling of CMOS has led to the increasing dominance of parasitic series resistance RPSR This high resistance negates the benefit of device scaling and will... Sarnet, D Debarre, J Boulmer, C Laviron, D Camel, J -L Santailler, and H Akhouayri, “Laser Thermal Processing Using an Optical Coating for Ultra Shallow Junction Formation,” Materials Science and Engineering B, vol 114-115, pp 105-108, Jul 2004 [1.17] S D Kim, C -M Park and J C S Woo, Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime – Part II: Quantitative Analysis,”... these components, RCON and RSDE have been numerously shown to be the largest contributing factor to RPSR, constituting over 40% each [1.3] Therefore, the challenging work of series resistance scaling should be focused on these two components 2 Figure 1.2 Schematic representation of S/D structure and parasitic series resistance components 1.2.1 S/D Resistance RSD and S/D Extension Resistance RSDE RSD is... NiSi [1.36] and NiSi2-xAlx [1.37] has already been demonstrated as potential candidates for such application 1.3 Objective of the Research The objective of this thesis is to address the parasitic series resistance issue which impedes the progress of current CMOS technology New materials and processes will be explored for potential solutions Their compatibility with strained technology and advanced structures... [1.34] A Kinoshita, Y Tsuchiya, A Yagishita, K Uchida, and J Koga, “Solution for High-Performance Schottky -Source/ Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation Technique,” in Symposium VLSI Technology Digest, 2004, pp 168-169 [1.35] A Kinoshita, C Tanaka, K Uchida, and J Koga, “High-Performance 50-nmGate-Length Schottky -Source/ Drain MOSFETs with Dopant-Segregation Junctions,”... introduction of the current technology Background information is provided for the parasitic series resistance issue Recent development to address the RSD, RSDE and RCON components of the parasitic series resistance issue is also presented in this chapter 8 Chapter 2 explores the feasibility of replacing the conventional Ni with Ni1-xAlx films These films were studied and their ФBn tuning correlated with the Al... P Absil, K De Meyer, M Jurxzak, and S Biesemans, “NMOS and PMOS Metal Gate Transistors with Junction Activated by Laser Annealing,” in International Symposium on VLSI Technology, System and Application, 2006, pp 1-2 [1.5] S Thompson, P Paclan, T Ghani, M Stettler, M Alavi, I Post, S Tyagi, S Ahmed, S Yang, and M Bohr, Source/ Drain Extension Scaling for 0.1µm and Below Channel Length MOSFETS,” in Symposium... 1.2.2 Silicide-S/D Contact Resistance RCON RCON arises mainly because of the formation of a Schottky-Barrier when the silicide and the S/D is in contact When an n-type Si with a work function less than that of the silicide are connected, electrons from the n-Si will pass into the silicide The two Fermi level will be forced into coincidence and a depletion region is formed, causing the bands bending upwards... pp.467472, Mar 2002 12 [1.18] S -D Kim, S Narasimha, and Ken Rim, “An Integrated Methodology for Accurate Extraction of S/D Series Resistance Components in Nanoscale MOSFETs,” in IEEE International Electron Device Meeting, 2005, pp 155-158 [1.19] K -I Goto, T Yamamoto, T Kubo, M Kase, Y Wang, T Lin, S Talwar, and T Sugii, “Ultra -Low Contact Resistance for Deca-nm MOSFETs by Laser Annealing,” in IEEE International . Silicon-Carbon Source/ Drain in MuGFETs 84 5.2 Future Work 85 Appendix A: Publication List 86 vi Advanced Source/ Drain Contact Engineering For Low Parasitic Series Resistance Abstract. Nickel-Aluminum Alloy Silicides for Contact Resistance Reduction 83 5.1.2 Impurity Engineering in NiSi and Pure Rare Earth Silicide for Contact Resistance Lowering 84 5.1.3 Integration. 1.1 Background 1 1.2 Parasitic Series Resistance R PSR 2 1.2.1 S/D Resistance R SD and S/D Extension Resistance R SDE 3 1.2.2 Silicide-S/D Contact Resistance R CON 5 1.3