ADVANCED SOURCE AND DRAIN CONTACT ENGINEERING FOR MULTIPLE-GATE TRANSISTORS RINUS TEK PO LEE NATIONAL UNIVERSITY OF SINGAPORE 2009 ADVANCED SOURCE AND DRAIN CONTACT ENGINEERING FOR MULTIPLE-GATE TRANSISTORS RINUS TEK PO LEE A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILIOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2009 Acknowledgements Pursuing a Ph.D. and embarking on a career in science/engineering has been a lifelong dream. It is not so much of the destination that is important but it is the journey towards achieving the goal, which shapes us. During my time at NUS, various outstanding individuals have guided my work, shaped my career goals, and added tremendous value to my education and I am grateful for their help. I would like to begin to acknowledge my Ph.D. advisors, Dr. Yeo Yee Chia and Dr. Chi Dong Zhi for their support throughout my graduate career at NUS. I have benefited immensely from their technical guidance and the intellectual freedom to pursue my research interests and directions in the field of nanotechnology. I would especially like to thank Dr. Yeo Yee Chia for his time and effort in guiding this dissertation as he is instrumental in shaping my graduate research career at NUS. In addition, I am grateful to Associate Professor Ganesh S. Samudra for his advice and timely suggestions throughout the course of my research. Special thanks also go to Dr. Wen Chin Lee for his guidance when I was a summer intern at Taiwan Semiconductor Manufacturing Company. I have benefited greatly from his vast experience in semiconductor technologies. I am also grateful for the guidance and discussions from the many outstanding graduate students of SNDL. Special thanks to Jason Liow and Tan Kian Ming for mentoring me in the initial phase of my research in the fabrication of multiple-gate device structures. I would also like to thank my “kopi kaki”, Andy Lim for all the time spent procrastinating and coffee binging at Dilys. Special thanks also go out to Alvin Koh for his tireless support in measurements and experiments during the crucial i submission deadlines. Thanks also go out to Lina Fang, Koh Shao Ming, Chin Hock Chun, Phyllis Lim, Wong Hoong Shing, Ang Kah Wee, Chui King Jien, Jiang Yu, Manu, Shen Chen, Liu Fang Yue, Yu Xiong Fei, Wang Xin Peng, Hsu Wen Wei, Hau Yu, and Gerry for their useful discussions and friendship over the last four years. I would also like to extend my deepest gratitude to my mum who has always been supportive of my academic endeavors even though she thinks that I have spent too much time in frivolous academic pursuits. To Lester, thank you for the encouragements and for being a brother that I could count on. Last but definitely not the least; I am eternally grateful for the steadfast support and love of my fiancée, Sharon throughout these years. The sacrifices that you have made in the support of my academic pursuits will never be forgotten. Thank you for the devotion. Thank you and God Bless ii Table of Content Acknowledgements i Table of Content iii Abstract vii List of Tables ix List of Figures x List of Symbols xxiv Chapter 1: Transistor Scaling 1.1 Introduction 1.2 Multiple-Gate Field-Effect-Transistor (MuGFET) Designs 1.2.1 Planar MuGFET 1.2.2 Vertical MuGFET 1.3 Technological Challenges for MuGFETs 1.4 Concept of Source/Drain Series Resistance Engineering 1.5 Objectives of Research 12 1.6 Thesis Organization 13 1.7 References 15 Chapter 2: Contact Engineering for Si Junction Technology 20 2.1 Introduction 20 2.2 Complementary MuGFETs with Ytterbium and Platinum Contacts 21 2.2.1 Device Concept and Fabrication 21 2.2.2 Ytterbium Silicide (YbSi1.8) Process Development 24 iii 2.3 2.2.3 Device Characterization: N-MuGETs with YbSi1.8 contacts 27 2.2.4 Platinum Silicide (PtSi) Process Development 29 2.2.5 Device Characterization: P-MuGFET with PtSi Contacts 32 2.2.6 Further Performance Optimization: P-MuGFET with Metal Gate 33 N-MuGFET with Nickel-Aluminide Disilicide Contacts 37 2.3.1 Process Concept 37 2.3.2 Nickel-Aluminum-Silicon Process Development 43 2.3.3 Device Fabrication and Characterization 47 2.3.4 Further Performance Optimization with Dopant Segregation 51 2.4 Summary 59 2.5 References 61 Chapter 3: Contact Engineering for Si1-yGey Junction Technology 65 3.1 Introduction 65 3.2 P-MuGFETs with Nickel Platinum Germanosilicide Contacts 67 3.2.1 Process Concept and Device Fabrication 67 3.2.2 Nickel Platinum Germanosilicide Process Development 70 3.2.3 Device Characterization and Analysis 76 P-MuGFETs with Platinum Germanosilicide Contacts 79 3.3.1 Process Concept and Device Fabrication 79 3.3.2 Platinum Germanosilicide Process Development 80 3.3.3 Device Characterization and Analysis 87 3.3 3.4 Summary 92 3.5 References 94 iv Chapter 4: Contact Engineering for Si1-yCy Junction Technology 99 4.1 Introduction 99 4.2 Nickel Silicide Contacts on Si1-yCy Junctions 101 4.2.1 Device Fabrication 101 4.2.2 Nickel Silicide:Carbon (NiSi:C) Process Development 105 4.3 N-MuGFETs with Nickel-Dysprosium-Silicide:Carbon Contacts 113 4.3.1 Process Concept 113 4.3.2 Nickel-Dysprosium-Silicon:Carbon Process Development 116 4.3.3 Device Characterization and Analysis 121 4.4 Summary 127 4.5 References 128 Chapter 5: Contact Engineering for Complementary MuGFETs Featuring Si1-yGey and Si1-yCy S/D Stressors 134 5.1 Introduction 134 5.2 Process Concept and Integration Flow 135 5.3 N-MuGFETs with Sulfur Segregated Platinum Silicide:Carbon Contacts 138 5.3.1 Device Fabrication 138 5.3.2 Sulfur Segregation Process Development 139 5.3.3 Device Characterization and Analysis 144 5.4 Summary 148 5.5 References 149 Chapter 6: Conclusion and Future Directions 151 6.1 151 Conclusion v 6.2 Contributions of this Thesis 152 6.3 Future Directions 156 6.4 References 159 Appendix A: Publication List 161 vi Abstract Advanced Source and Drain Contact Engineering for Multiple-Gate Transistors by Rinus Tek Po Lee Doctor of Philosophy − Electrical and Computer Engineering National University of Singapore Geometrical scaling is reaching its fundamental limits after four decades of continuous downsizing of device dimensions to increase the cost per function of integrated circuits. As of the writing of this thesis, the 22 nm technology generation is under-going development at leading semiconductor companies. These companies have indicated that multiple gate transistor designs are promising architectures for extending device performances. These transistors offer improved electrostatic control and steeper subthreshold swings compared to planar transistor designs. However, the manufacturability of these transistor designs is still an issue as they suffer from a significant increase in parasitic capacitances and resistances due to its inherent design. In this thesis, a novel metal alloy concept for electron (ΦBN) and hole barrier (ΦBP) height engineering was developed to address the escalating issue of parasitic source/drain (S/D) series resistances (or external resistance) in nanoscale multiple-gate field-effect-transistors (MuGFETs). Various process integration challenges relating to technology demonstrations for the proposed concept on N- and P-channel MuGFETs were identified and addressed in this thesis. For N-channel MuGFETs (N-MuGFETs), new materials such as ytterbium silicide, nickel aluminide disilicide, and nickel dysprosium silicide:carbon were developed for external resistance (REXT) reduction. The key characteristics of these new materials were determined and identified in this vii thesis. Technology demonstrations of these new materials integrated as S/D contacts in N-MuGFETs exhibit significant drive current enhancement. This affirms the effectiveness of the designed concept for ΦBN engineering with low work function elements. For complementary P-channel MuGFETs (P-MuGFETs), high work function elements were used to engineer the S/D contact ΦBP. A significant drive current enhancement of 21 % was achieved in these P-MuGFETs compared to control devices. This firmly established the feasibility of the proposed metal alloy concept to engineer both ΦBN and ΦBP to reduce device REXT. However, the metal alloy concept requires the selection and optimization of two different metal contacts to achieve low ΦBN and ΦBP for N- and P-MuGFETs, respectively. This increases process complexity and cost in high-volume manufacturing. This thesis then proposed an alternative concept exploiting the formation of interfacial dipoles with sulfur segregation to engineer the ΦBN of a high work function material (i.e. material with low ΦBP). This opens up the possibility of implementing a single contact metal silicide process to independently control the ΦBN and ΦBP for N- and P-MuGFETs, respectively. Technology demonstration with this concept achieved significant drive current enhancement of 45 % for N-MuGFETs due to the segregation of sulfur at the contact-to-semiconductor interface. viii [9] A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. De Meyer, “Analysis of the parasitic S/D resistance in multiple-gate FETs,” IEEE Trans. on Electron Devices, vol. 52, no. 6, pp. 1132 – 1140, Jun. 2005. 150 Chapter Conclusion and Future Directions 6.1 Conclusion Continuous transistor downsizing has met immense challenges which have to be surmounted in order to realize the full potential of complementary metal-oxidesemiconductor (CMOS) technology. New materials and device technology will have to be developed to extend device scaling into the sub-10 nm regime. It has been indicated in recent literature [1] – [2] that multiple gate field-effect-transistor (MuGFETs) are promising architectures for extending device performance. MuGFETs offer improved electrostatic control and short-channel control compared to planar transistors [3], [4]. However, the designs of MuGFETs induce a significant increase in parasitic capacitances and resistances due to its dimensional structure [5]. Hence, it is crucial that parasitic capacitances and resistances associated with the MuGFET be reduced to enable the adoption of this architecture for future CMOS technology generations. It is the objective of this thesis to explore new materials and process technologies to address the escalating issue of source/drain (S/D) series resistances (or external resistances) in nanoscale MuGFETs. Various process technologies coupled with new materials have been proposed/developed and experimentally realized in this thesis for N- and P-channel MuGFETs. In particular, this thesis introduces the concept of metal alloy in nickel silicide to engineer the electron- and hole-barrier heights of the S/D contacts to reduce device external resistances. This will ultimately result in enhanced device performances. The seminal contributions of this thesis are listed in Table 6.1 and highlighted in the next section. 151 Table 6.1 A summary of barrier height reduction and drive current enhancement achieved with the various new materials and barrier height engineering approaches demonstrated in this thesis. Barrier Height Engineering Approaches Barrier Height Reduction (%) (eV) Drive Current Enhancement (%) 35 41 32 30 - - 53 87 49 45 40 34 18 21 A. N-Channel MuGFETs YbSi1.8 NiSi1.80Al0.20 NiSi1.80Al0.20 with As+ segregation B. P-Channel MuGFETs PtSi with FUSI Pt3Si Metal Gate C. Strained N-Channel MuGFETs with Si:C S/D Ni[Dy]Si:C PtSi:C with S+ segregation D. Strained P-Channel MuGFETs with SiGe S/D Ni0.90Pt0.10SiGe PtSiGe 6.2 Contributions of this Thesis A. Complementary MuGFETs with Schottky-Barrier Source/Drain Contacts In this technology demonstration, we fabricated sub-30 nm N- and P-channel MuGFETs integrated with Schottky-barrier source/drain (S/D) junctions. This work developed two innovative anneal process to aid in the development of a self-aligned process for ytterbium and platinum silicides. The fabricated transistors exhibit good device characteristics with state-of-the-art of current drives. The results of this work will be useful for the further development of new lanthanide materials to engineer the electron barrier heights for the S/D contacts of aggressively scaled MuGFETs. 152 B. N-channel MuGFETs with Nickel Aluminide Disilicide Contacts In this technology demonstration, the concept of metal alloy with low work function elements in nickel silicide (NiSi) for electron barrier height (ΦBN) engineering was first introduced. Our results revealed that the addition of metal alloys can affect the formation and morphological stability of NiSi substantially. It was shown that the addition of aluminum (Al) in NiSi forming NiSi1.80Al0.20 provided the best trade-off in terms of resistivity (ρ) and ΦBN to maximize device performance. Device demonstrations with NiSi1.80Al0.20 contacts provided a 32 % enhancement in drive current performance when compared to control devices with NiSi contacts. We further assess the compatibility NiSi1.80Al0.20 with dopant segregation to realize an ultra low ΦBN contact technology option. This combinational approach achieved a conduction band edge ΦBN of 0.133 eV for NiSi1.80Al0.20. The results of this work ascertain the feasibility of the proposed metal alloy concept for ΦBN engineering to reduce device external resistance for aggressively scaled MuGFETs. C. P-channel MuGFETs with Nickel Platinum and Platinum Germanosilicide Contacts In this technology demonstration, we utilized the concept of metal alloy and incorporated the high work function element platinum (Pt) into NiSi for hole barrier height (ΦBP) engineering. We show that the addition of Pt enhances nickel germanosilicide (NiSiGe) morphological stability and reduces ΦBP for superior Pchannel MuGFET operation. When compared to NiSiGe, Ni0.90Pt0.10SiGe contacts give rise to an overall 18 % enhancement in drive current performance. This is attributed to the suppression of agglomeration and germanium out-diffusion, and reduced external resistance (REXT ) ~15 % with the addition of Pt. We also evaluate the option of utilizing pure Pt to form platinum germanosilicide (PtSiGe) contacts in the S/D regions 153 for device integration. The material and electrical characteristics of these pure PtSiGe contacts were investigated extensively to ascertain its suitability for device integration. It was found that PtSiGe has a low ΦBP of 0.215 eV with superior thermal and surface morphological stability compared to conventional NiSiGe. The integration of these low ΦBP PtSiGe contacts in the S/D regions of P-MuGFETs achieves a 27 % reduction in device REXT compared to NiSiGe. This gives a statistical 21% enhancement in saturation drive current (IDsat). The higher IDsat were achieved while maintaining comparable subthreshold swing and drain-induced barrier lowering values to that of NiSiGe contacts. This work illustrates the potential of forming low ΦBP contacts with Pt-based contacts in the S/D regions of MuGFETs to extend device performance for future technology nodes. D. N-channel MuGFETs with Nickel-Silicide:Carbon Contacts In this technology demonstration, we first examined the characteristics of nickel silicide (NiSi) formed on silicon:carbon. We established that nickel silicide:carbon (NiSi:C) contacts are compatible with silicon:carbon (Si:C or Si1-yCy) junction technology. This demonstrates that NiSi:C is a suitable baseline contact option to devices with Si1-yCy S/D stressors. We also showed that bandgap (Eg) narrowing due to substitutional carbon (Csub) contributes a 10.3 % (69 meV) reduction in electron barrier height (ΦBN) for NiSi formed on Si1-yCy for 1.0 % Csub. This carboninduced ΦBN lowering can be exploited as a process knob for ΦBN optimization in devices with Si1-yCy S/D stressors. The metal alloy concept with low work function elements for ΦBN engineering was also applied to NiSi:C contacts in this demonstration. We found that dysprosium (Dy) provides the most effective reduction in ΦBN among the elements investigated 154 forming Ni[Dy]Si:C. The underlying mechanisms for this effective reduction of ΦBN were clarified. We postulate that charge transfer at the Ni[Dy]Si:C/Si0.99C0.01 interface due to the presence of a dysprosium interlayer leads to the reduction in ΦBN for Ni[Dy]Si:C contacts. This reduction of ΦBN for Ni[Dy]Si:C contacts translates to an effective 41 % reduction in device REXT in N-MuGFETs with Si1-yCy S/D stressors, resulting in improved drive current performance. These results open new avenues to optimize the Si1-yCy contact interface for extending transistor performance in future technological generations. E. N-MuGFETs with Sulpfur Segregated Platinum Silicide:Carbon Contacts In this technology demonstration, we show that by employing sulpfur (S) segregation at the platinum silicide:carbon/silicon:carbon (PtSi:C/Si:C) interface, the lowest electron barrier height (ΦBN) of 0.11 eV reported to date for Pt-based silicides was achieved. We ascribed this remarkable ΦBN reduction to the formation of dipoles at the interface in the presence of S. PtSi:C with S exhibit a 51 % improvement in external resistance. This leads to superior saturation drive current (IDsat) performance and contributes a 45 % gain in IDsat for devices having PtSi:C with S. Our results illustrate the potential of employing S segregation to realize a highly manufacturable single contact metal silicide process to independently optimize the electron and hole barrier height at the S/D contact interface. 155 6.3 Future Directions In summary, this thesis focuses on developing solutions to arrest the escalating dominance of parasitic external resistances (REXT) in advanced MuGFET designs. This thesis has conceptualized and embarked on the development of several exploratory concepts and technology options to reduce device REXT and improve transistor drive current performance. Preliminary assessment has verified that the concept of electron (ΦBN) and hole barrier height (ΦBP) engineering is a promising approach to reduce device REXT. Our extensive review of various exploratory contact technology options in this thesis and those available in the literature have consolidated the different 0.8 0.5 Hole Barrier Height ΦB (eV) n-Si(100) NiSi reference 0.7 Ν Electron Barrier Height ΦΒ (eV) approaches available for ΦBN and ΦBP engineering as shown in Figure 6.1. 0.5 0.4 0.3 0.2 0.1 0.0 NiErSi x P 0.6 NiYbSi x NiTiSix NiAlSix TbSix NiYbSix Ni + N Ni + As + DySi x ErSi x YbSix + CoSi + As + + NiSi + Se + NiSi + S + NiAlSix + As NiSbSix -50 50 100 150 200 Film Resistivity ρfilm (µΩ⋅cm) p-Si(100) NiSi reference NiSi 0.4 NiSi + In + 0.3 Pd2 Si PtSi 0.2 PtSi + In + + IrSi 0.1 NiSi + Al + PtSi + B + NiSi + B 0.0 10 20 30 40 Film Resistivity ρfilm (µΩ⋅cm) (b) (a) Fig. 6.1 Summary plot of barrier heights versus film resistivity for the various approaches to engineer the (a) electron and (b) hole barrier heights in the S/D contact for N- and P-channel devices, respectively. It is evident that the segregation approach yields the lowest barrier heights and resistivities for both n- and p-doped Si substrates. 156 The data clearly shows that the segregation approach is the most promising technique among the various contact options as it has the best trade-off in terms of resistivity and barrier heights for device integration. However, a more rigorous and in-depth analysis of the segregation approach has to be dealt with to ascertain the effectiveness and robustness of this approach for high-volume manufacturing. In addition, the inevitable implementation of alternative substrates for enhanced device performance will also open up opportunities for research and development in new contact technologies to these advanced substrates. Some of these suggestions for future directions in the field of S/D contact engineering are highlighted in this section. A. Extension of the Segregation Approach for CMOS Applications In this thesis, we demonstrated that S segregation can be exploited to engineer the electron barrier height of platinum silicide:carbon (PtSi:C). This achieves a CMOS process without the complexity of a dual metal silicide process. However, the use of precious metals such as platinum in high-volume manufacturing should be minimized as much as possible to maximize cost-performance benefits. An alternative approach that uses a dual segregation technique with conventional nickel silicide (NiSi) will be highly desired. A viable approach will be the use of sulfur or selenium [6] for Nchannel transistors and Al [7] for P-channel transistors. Hence, an in-depth analysis of the segregation mechanisms and the opposing effects of these segregation implants on the electron or hole barrier heights at the transistor source/drain contacts and device external resistances will be extremely useful for device researchers in the 22 nm node and beyond developmental teams. 157 B. Contact Engineering for Germanium Devices Fermi-level pinning is a potential technological roadblock in the development of source/drain designs for N-channel germanium (Ge) devices [8]. The concept of metal alloy for electron barrier height engineering developed in this thesis could be extended to the Ge S/D platform for evaluation. In addition, sulfur segregation with nickel germanide has been demonstrated to be effective for electron barrier height engineering in contact structures [9]. Further development in this area should focus on the segregation mechanism to establish the effectiveness of this approach for Ge devices. C. Contact Engineering for III-V Devices The renewed interested in III-V devices for metal-oxide-semiconductor applications [10], [11] have opened up opportunities as well as the need to develop source/drain (S/D) contact options to these devices. As of the writing of this dissertation, no solutions exist for a self-aligned approach to integrate S/D contacts in III-V devices. The concepts developed in the preceding chapters of this thesis could provide insights to the development and selection of elements for alloyed contacts on III-V devices. The use of the segregation approach for contact engineering in III-V devices is also a feasible technique that needs to be investigated as well. 158 6.4 References [1] M. Guillorn, J. Chang, A. Bryant, N. Fuller, O. Dokumaci, X. Wang, J. Newbury, K. Babich, J. Ott, B. Haran, R. Yu, C. Lavoie, D. Klaus, Y. Zhang, E. Sikorski, W. Graham, B. To, M. Lofaro, J. Tornello, D. Koli, B. Yang, A. Pyzyna, D. Neumeyer, M. Khater, A. Yagishita, H. Kawasaki, and W. Haensch, “FinFET performance advantage at 22nm: An AC perspective,” Symposium on VLSI Technology, pp. 12 –13, 2008. [2] B. S. Haran , A. Kumar, L. Adam, J. Chang, V. Basker, S. Kanakasabapathy, D. Horak, S. Fan, J. Chen, J. Faltermeier, S. Seo, M. Burkhardt, S. Burns, S. Halle, S. Holmes, R. Johnson, E. McLellan, T. M. Levin, Y. Zhu, J. Kuss, A. Ebert, J. Cummings, D. Canaperi, S. Paparao, J. Arnold, T. Sparks, C. S. Koay, T. Kanarsky, S. Schmitz, K. Petrillo, R. H. Kim, J. Demarest, L. Edge, H. Jagannathan, M. Smalley, N. Berliner, K. Cheng, D. LaTulipe, C. Koburger, M. Raymond, M. Colburn, T. Spooner, V. Paruchuri, W. Haensch, D. McHerron, B. Doris, “22 nm Technology Compatible Fully Functional 0.1 m2 6T-SRAM Cell,” International Electron Device Meeting Tech. Dig., pp. 1029 – 1031, 2008. [3] D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takedea, “A fully depleted lean-channel transistor (DELTA) – A novel vertical ultra thin SOI MOSFET,” International Electron Device Meeting Tech. Dig., pp. 833 – 836, 1989. [4] Y.K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.J. King, J. Bokor, and C. Hu, “Sub-20 nm CMOS FinFET technologies,” International Electron Device Meeting Tech. Dig., pp. 719 – 722, 2000. [5] J. Kedzierski, M. Ieong, E. Nowak, T.S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H.S.P. Wong, “Extension and source/drain design for high performance FinFET devices,” IEEE Trans. on Electron Devices, vol. 50, no. 4, pp. 952 – 958, Apr. 2003. [6] H.-S. Wong, F.-Y. Liu, K.-W. Ang, G. Samudra, and Y.-C. Yeo, “Novel nickel silicide contact technology using selenium segregation for SOI N-FETs with silicon carbon source/drain stressors,” IEEE Electron Device Letters, vol. 29, no. 8, pp. 841 – 844, 2008. 159 [7] M. Sinha, R. T. P. Lee, K.-M. Tan, G.-Q. Lo, E. F. Chor, and Y.-C. Yeo, “Novel aluminum segregation at NiSi/p+Si source/drain contact for drive current enhancement in p-channel FinFETs,” IEEE Electron Device Letters, vol. 30, no. 1, pp. 85 – 87, 2009. [8] M. Kobayashi, A. Kinoshita, K. Saraswat, H. S. P. Wong, and Y. Nishi, “Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET,” Symposium on VLSI Technology, pp. 54 – 55, 2008. [9] K. Ikeda, Y. Yamashita, N. Sugiyama, N. Taoka, amd S.-I. Takagi, “Modulation of NiGe/Ge Schottky barrier height by sulfur segregation during Ni germanidation,” Applied Physics Letters, vol. 88, no. 15, 152115, Apr. 2006. [10] Y. Xuan, Y. Q. Wu, T. Shen, T. Yang, and P. D. Ye, “High performance submicron inversion-type enhancement-mode InGaAs MOSFETs with ALD Al2O3, HfO2 and HfAlO as gate dielectrics,” International Electron Device Meeting Tech. Dig., pp. 637 – 640, Dec. 2007. [11] H.-C. Chin, M. Zhu, Z.-C. Lee, X. Liu, K.-M. Tan, H. K. Lee, L. Shi, L.-J. Tang, C.-H. Tung, L.-S. Tan, and Y.-C. Yeo, “A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs n-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack,” International Electron Device Meeting Tech. Dig., pp. 383 – 386, Dec. 2008. 160 Appendix A List of Publications Journal Publications [1] R. T. P. Lee, Andy E.-J. Lim, K. M. Tan, T. Y. Liow, G. Q. Lo, G. S. Samudra, D. Z. Chi, and Y.-C. Yeo, “N-channel FinFETs with 25 nm gate length and Schottky-barrier source and drain featuring ytterbium silicide,” IEEE Electron Device Letters, vol. 28, no. 2, pp. 164 – 167, Feb. 2007. [2] R. T. P. Lee, K. M. Tan, T. Y. Liow, C. S. Ho, S. Tripathy, D. Z. Chi, and Y. C. Yeo, “Probing the ErSi1.7 Phase Formation by Micro-Raman Spectroscopy,” J. Electrochemical Society, vol. 154, no. 5, pp. H361 − H364, May 2007. [3] R. T. P. Lee, L. T. Yang, T. Y. Liow, K. M. Tan, A. E.-J. Lim, K. W. Ang, D. M. Y. Lai, K. M. Hoe, G. Q. Lo, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Nickelsilicide:carbon contact technology for n-channel MOSFETs with silicon-carbon source/drain,” IEEE Electron Device Letters, vol. 29, no. 1, pp. 89 – 92, Jan. 2008. [4] A. T. Y. Koh, R. T. P. Lee, A. E.-J. Lim, D. M. Y. Lai, D. Z. Chi, K. M. Hoe, N. Balasubramanian, G. S. Samudra, and Y. C. Yeo, “Nickel-aluminum alloy silicides with high aluminum content for contact resistance reduction and integration in nchannel field-effect transistors,” J. Electrochemical Society, vol. 155, no. 3, pp. H151 − H155, Mar. 2008. [5] R. T. P. Lee, T. Y. Liow, K. M. Tan, A. E.-J. Lim, A. T. Y. Koh, G. Q. Lo, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Achieving conduction band-edge Schottky barrier height for arsenic-segregated nickel aluminide disilicide and implementation in FinFETs with ultra narrow fin widths,” IEEE Electron Device Letters, vol. 29, no. 4, pp. 382 – 385, Apr. 2008. [6] R. T. P. Lee, K. M. Tan, A. E.-J. Lim, T. Y. Liow, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “P-channel tri-gate FinFETs featuring Ni1-yPtySiGe source/drain contacts for enhanced drive current performance,” IEEE Electron Device Letters, vol. 29, no. 5, pp. 438 – 441, May 2008. 161 [7] A. T. Y. Koh, R. T. P. Lee, F. Y. Liu, T. Y. Liow, K. M. Tan, X. Wang, G. S. Samudra, D. Z. Chi, N. Balasubramanian, and Y. C. Yeo, “Pulsed laser annealing of silicon-carbon source/drain in multiple-gate transistors for enhanced dopant activation and high substitutional carbon concentration,” IEEE Electron Device Letters, vol. 29, no. 5, pp. 464 – 467, May 2008. [8] M. Sinha, R. T. P. Lee, K. M. Tan, G. Q. Lo, E. F. Chor, and Y. C. Yeo, “Novel aluminum segregation at NiSi/p+Si source/drain contact for drive current enhancement in p-channel FinFETs,” IEEE Electron Device Letters, vol. 30, no. 1, pp. 85 – 87, Jan. 2009. [9] R. T. P. Lee, A. E.-J. Lim, K. M. Tan, T. Y. Liow, D. Z. Chi, and Y. C. Yeo, “Sulfur induced PtSi:C/Si:C Schottky barrier height lowering for realizing n-channel FinFETs with reduced external resistance,” IEEE Electron Device Letters, vol. 30, no. 5, pp. 472 – 474, May 2009. [10] M. Sinha, R. T. P. Lee, A. Lohani, S. Mhaisalkar, E. F. Chor, and Y. C. Yeo, “Achieving Sub-0.1 eV hole Schottky barrier height for NiSiGe on SiGe by aluminum segregation,” J. Electrochemical Society, vol. 156, no. 4, pp. H233 − H238, Apr. 2009. [11] R. T. P. Lee, D. Z. Chi, and Y. C. Yeo, “Platinum germanosilicide as source/drain contacts in p-channel fin-field effect transistors (FinFETs),” IEEE Trans. on Electron Devices, vol. 56, no. 7, pp. 1458 – 1465, Jul. 2009. [12] P. S. Y. Lim, R. T. P. Lee, M. Sinha, D. Z. Chi, and Y. C. Yeo, “Effect of substitutional carbon concentration on Schottky-barrier height of nickel silicide formed on epitaxial silicon-carbon films,” J. Applied Physics, vol. 106, 2009. [13] R. T. P. Lee, A. T. Y. Koh, K. M. Tan, T. Y. Liow, D. Z. Chi, and Y. C. Yeo, “The role of carbon and dysprosium in Ni[Dy]Si:C contacts for Schottky barrier height reduction and application in n-channel MOSFETs with Si:C source/drain stressors,” IEEE Trans. on Electron Devices, vol. 56, no. 11, Nov. 2009. 162 Conference Publications [14] R. T. P. Lee, T. Y. Liow, K. M. Tan, K. W. Ang, K. J. Chui, G. Q. Lo, G. S. Samudra, D. Z. Chi and Y. C. Yeo, “Process-Induced Strained P-MOSFET Featuring NickelPlatinum Silicided Source/Drain,” Materials Research Society Spring Meeting, Apr. 2006. [15] R. T. P. Lee, K. M. Tan, A. E.-J. Lim, T. Y. Liow, G. Q. Lo, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Sub-30 nm p-channel Schottky source/drain FinFETs: Integration of Pt3Si FUSI metal gate and high-k dielectric,” Solid State Device and Materials Conf. Ext. Abst., pp. 1110 – 1111, 2006. [16] R. T. P. Lee, T. Y. Liow, K. M. Tan, A. E.-J. Lim, H. S. Wong, P. C. Lim, D. M. Y. Lai, G. Q. Lo, C. H. Tung, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Novel nickelalloy silicides for source/drain contact resistance reduction in n-channel multiple-gate transistors with sub-35 nm gate length,” International Electron Device Meeting Tech. Dig., pp. 851 – 854, Dec. 2006. [17] R. T. P. Lee, K. M. Tan, T. Y. Liow, A. E.-J. Lim, G. Q. Lo, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Sub-30 nm FinFETs with Schottky-barrier source/drain featuring complementary metal silicides and fully-silicided gate for p-FinFETs,” Materials Research Society Spring Meeting, Apr. 2007. [18] R. T. P. Lee, L. Yang, K. W. Ang, T. Y. Liow, K. M. Tan, A. S. W. Wong, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Material and electrical characterization of nickel silicide-carbon as contact metal to silicon-carbon source and drain stressors,” Materials Research Society Spring Meeting, Apr. 2007. [19] R. T. P. Lee, T. Y. Liow, K. M. Tan, A. E.-J. Lim, C. S. Ho, K. M. Hoe, T. Osipowicz, G. Q. Lo, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Novel epitaxial nickel aluminide-silicide with low Schottky-barrier and series resistance for enhanced performance of dopant-segregated source/drain MuGFETs,” Symposium on VLSI Technology, pp. 108-109, Dec. 2007. 163 [20] R. T. P. Lee, K. M. Tan, A. E.-J. Lim, T. Y. Liow, X. C. Chen, M. Zhu, A. T. Y. Koh, K. M. Hoe, S. Y. Chow, G. Q. Lo, G. S. Samudra, D. Z. Chi, Y. C. Yeo, “Contact technology employing nickel-platinum germanosilicide alloys for p-channel FinFETs with silicon-germanium source and drain stressors,” Solid State Device and Materials Conf. Ext. Abst., pp. 1042 – 1043, 2007. [21] R. T. P. Lee, A. T. Y. Koh, F. Y. Liu, W. W. Fang, T. Y. Liow, K. M. Tan, P. C. Lim, A. E.-J. Lim, M. Zhu, K. M. Hoe, C. H. Tung, G. Q. Lo, X. Wang, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Route to Low Parasitic Resistance in MuGFETs with SiliconCarbon Source/Drain: Integration of Novel Low Barrier Ni(M)Si:C Metal Silicides and Pulsed Laser Annealing,” International Electron Device Meeting Tech. Dig., pp. 685 – 688, Dec. 2007. [22] R. T. P. Lee, F. Y. Liu, K. M. Tan, A. E.-J. Lim, T. Y. Liow, S. Tripathy, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Formation of nickel-based germanosilicide contacts on silicon-germanium-tin (Si1-x-yGexSny) source/drain stressors,” Materials Research Society Spring Meeting, May. 2008. [23] R. T. P. Lee, A. T. Y. Koh, W. W. Fang, K. M. Tan, A. E.-J. Lim, T. Y. Liow, S. Y. Chow, A. M. Yong, H. S. Wong, G. Q. Lo, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Novel and cost-efficient single metallic silicide integration solution with dual Schottky-Barrier achieved by Aluminum inter-diffusion for FinFET CMOS technology with enhanced performance,” Symposium on VLSI Technology, pp. 28 – 29, Jun. 2008. [24] P. S. Y. Lim, R. T. P. Lee, A. E.-J. Lim, A. T. Y. Koh, M. Sinha, D. Z. Chi, and Y. C. Yeo, “Schottky-barrier height tuning of nickel silicide on epitaxial silicon-carbon films with high substitutional carbon content,” Solid State Device and Materials Conf. Ext. Abst., pp. 692 – 693, 2008. [25] M. Sinha, R. T. P. Lee, S. N. Devi, G. Q. Lo, E. F. Chor, and Y. C. Yeo, “P-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction,” International Symposium on VLSI Technology, Systems and Applications, pp. 74 – 75, Apr. 2009. 164 [26] M. Sinha, R. T. P. Lee, S. Devi, G. Q. Lo, E. F. Chor and Y. C. Yeo, “Integration of Al segregated NiSiGe/SiGe source/drain contact technology in p-FinFETs for drive current enhancement,” 215th Electrochemical Society Meeting, May 2009. [27] M. Sinha, R. T. P. Lee, S. N. Devi, G. Q. Lo, E. F. Chor, and Y. C. Yeo, “Single silicide comprising nickel-dysprosium alloy for integration in p- and n- FinFETs with independent control of contact resistance by aluminum implant,” Symposium on VLSI Technology, pp. 106 – 107, Jun. 2009. [28] R. T. P. Lee, D. Z. Chi, and Y. C. Yeo, “Sulfur segregation at the platinum silicide/silicon:carbon interface for electron barrier height reduction: An approach to enable independent control of contact resistances for n- and p-channel FinFETs with a single metal silicide,” European Materials Research Society Spring Meeting, Jun. 2009. . 165 [...]... to form the device channel 1.2.1 Planar MuGFET In the formation of a planar MuGFET, the back -gate is patterned and formed prior to bonding A conventional transistor structure is then fabricated on the bonded region and aligned to the back -gate In this process, a single photolithography step is used to define both gates The technological challenge for this design is the alignment of the top and back gates... of PtSi and Pt3Si treated with aqua regia at 80 oC (a) PtSi line formed with a single step anneal in N2 (b) Pt3Si line formed with a single step anneal in N2, and (c) Pt3Si formed with a two-step anneal, first in N2 and followed by O2 Fig 2.12 34 Cross sectional schematic show the modified process technology developed in this work (a) Formation of Pt3Si FUSI gate and PtSi S/D contacts... channel strain engineering holds great promise for the continual improvement of transistor drive current performance [19], [20] For this reason, in order for MuGFET technology to be adopted for highvolume manufacturing, it must be compatible with strain engineering techniques as it is a powerful performance booster Intensive research efforts are ongoing to ascertain the compatibility of strain engineering. .. NiSi1.80Al0.20, As+ segregated NiSi and As+ segregated NiSi1.80Al0.20 junctions on p-doped Si Fig 2.32 55 ID − VG characteristics show comparable control of short-channel effects for the devices integrated with As+ segregated NiSi and NiSi1.80Al0.20 contacts Inset shows the extracted REXT values for devices with As+ segregated NiSi and NiSi1.80Al0.20 contacts 57 Fig 2.33... with NiSiGe and PtSiGe contacts Comparable subthreshold swing and DIBL were observed (b) ID – VD family of curves shows substantial IDsat enhancement for PMuGFET device with PtSiGe contacts over the control FinFET device with NiSiGe contacts Fig 3.17 88 IOFF – IDsat characteristics comparing the drain currents of P-MuGFETs with NiSiGe and PtSiGe contacts A 21... densities for contacts of NiSi, PtSi:C with and without S For each contact device split, a total of 21 samples were measured All measurements were made at 1 V in reverse bias at room temperature Fig 5.8 144 ID – VG transfer characteristics show comparable DIBL and SS for NMuGFETs with and without S This implies that the devices have comparable device dimensions and the... film resistivity for the various approaches to engineer the (a) electron and (b) hole barrier heights in the S/D contact for N- and P-channel devices, respectively It is evident that the segregation approach yields the lowest barrier heights and resistivities for both n- and p-doped Si substrates xxiii 156 List of Symbols Symbol Description Unit Cox Capacitance of gate oxide F Gm Transconductance... potential, depletion width, and short channel effects [1] Furthermore, permittivity of the gate oxide, doping concentration in the gate and source/ drain regions and mobility of the channel materials are also not correlated with geometrical scaling [1] Hence, it is crucial that alternative approaches to geometrical scaling be developed to extend the limits of device performance for future CMOS technology... literature for the multiple- gate structure such as MuGFET, FinFET, Trigate FET However, the device operation remains similar among these variants with only the number of gates as the distinguishing factor 2 z y x Gate Electrode Spacer Si-Fin Insulator Substrate Fig 1.1 Schematic representation of a triple -gate structure with the gate electrode encompassing the three sidewalls of the silicon fin to form the... 2.1 Summary of key parameters for the elements selected to engineer the ΦBN of NiSi in our proposed concept of metal alloying Table 2.2 Summary of hole barrier heights (ΦBP) and electron barrier heights (ΦBN) for the different contacts investigated in this section Table 3.1 38 56 Comparison of ΦBP, ΦBN, n, and ρ for NiSiGe and Ni1-yPtySiGe films formed at 450 oC ΦBP was extracted . vii Abstract Advanced Source and Drain Contact Engineering for Multiple -Gate Transistors by Rinus Tek Po Lee Doctor of Philosophy − Electrical and Computer Engineering National University. 2009 ADVANCED SOURCE AND DRAIN CONTACT ENGINEERING FOR MULTIPLE -GATE TRANSISTORS RINUS TEK PO LEE A THESIS SUBMITTED FOR THE DEGREE. ADVANCED SOURCE AND DRAIN CONTACT ENGINEERING FOR MULTIPLE -GATE TRANSISTORS RINUS TEK PO LEE