102 Chapter 4 DC-DC Conversion Architectures board level design. The digitalization of power is progressing in each of these domains at different speeds, which causes much confusion. Digital Power Chip Design In recent years a number of startups have tried to crack the computing market space at the chip level with digital implementations of the tradi- tional analog PWM modulator design, without much success. These implementations have found some space in high-end server blades appli- cations that are low volume and tolerate higher cost. In handsets, the increase in power levels is due to packing more ele- mentary building blocks on-die. Such elementary building blocks have rel- atively low power consumption by themselves, but in large numbers add up to a considerable amount of power. The most complex power manage- ment units (PMUs) built today clearly show that LDOs and switchers remain primarily analog. On top of traditional analog, a good dose of digi- tal is needed for communications and sequencing, and is implemented with architectures ranging from state machines to microcontrollers. Digital Power IC Processes As far as integrated circuits are concerned, the leading edge of the analog world long ago moved from pure analog to mixed analog and digital. Every VRM chip marries an on-die Digital to Analog Converter (DAC) to an analog switching regulator; the same way every PMU mixes analog and digital blocks. The move to mixed signal-the combination of analog and digital on the die-is a revolution that began around 1980. It started tenta- tively within the bipolar world with Integrated Injection Logic (I2L) logic gates and then fully blossomed with bipolar, CMOS, and DMOS (BCD) mono1 i thic processes. Today, the leading monolithic power companies have BCD mixed sig- nal processes. These companies-as leaders often do-position them- selves as solution-oriented, utilizing the most appropriate process, components, and techniques for the task at hand. BCD processes can use bipolar for precision, CMOS for signal den- sity, and DMOS for power density. Leading BCD is today in its 7‘h gener- ation at 0.18 pm and soon it will be at 0.12 pm (BCD VIII): this is only two nodes away from the CPU roadmap at 0.65 nm by the end of 2005. Still, these companies understand the trade-off in terms of mask count and cost and, therefore, keep alive simpler or “traditional” analog processes that in specific applications-particularly single functional building blocks-may result in more cost-effective designs. Digital Power 103 Board-Level Digital Power Telecom and Datacom applications like Point Of Loud (POL) are the areas where digital power may find the best niche. (Digital power in this case refers to power regulation equipped with a communication bus that allows for flexible set-output voltage, frequency compensation type, etc.) Leading power supply companies are battling for dominance of this new market. Conclusion At the board level, digital power seems to have found a hot niche in POL applications. Digital implementation of analog algorithms in silicon makes sense is some cases, like providing silicon in support of digital POL power, while in others it does not. The digitalization of power happened twenty years ago with BCD processes; today it is happening in the high- performance niches of computing power at the chip architecture level, and it will probably happen soon at the board level with POLS. As the saying goes, the next big thingdigital power in this instance-is already here. It is just not uniformly distributed. Perhaps more importantly for IC compa- nies, a good process portfolio, which includes processes like BCD, takes us beyond the debate of digital versus analog and allows us to focus on solutions. Fast Switchmode Regulators and Digital Control The bulk of the CPU power regulation volumes are in the PC motherboard market, a fiercely competitive market dominated by the Taiwanese motherboard manufacturers operating on a relatively short-term horizon and driven by cost. Accordingly, these motherboards have the lowest pos- sible bill of materials. It follows that the “sweet spot” for power is a volt- age regulator built around some very resilient technologies based on the buck converter, which continues to reinvent itself (from buck to sync buck to multiphase to .) and thus far defies any new proposed architecture, and the electrolytic capacitor, which in its latest reincarnation, Aluminum- Polymer, keeps the emergence of ceramic caps at bay. More precisely, huge amounts (mF) of “bulk” capacitors are employed in the design of buck converters to supply most of the energy during transient (the time it takes the feedback loop to respond) while a minimum number of ceramics are employed nearby the CPU socket for quasi-instantaneous response. Modern specifications for CPU regulators require operation inside a tight voltage band (50 mV), while the source of degradation of the regulators is the Equivalent Series Resistance (ESR, in mQ) of the output capacitors. Consequently at 50 A, the tolerable ESR has to be 40 mV/50 A = 1 mQ. 104 Chapter 4 DC-DC Conversion Architectures Until now the $/mQ figure of “merit” for electrolytic remains unsur- passed-namely the lowest-and this simple fact explains why any fast converter technology thrown at this niche does not stick, despite the prom- ise to eliminate the “bulky” electrolytics. n Discrete Duty Ratio t ,. !,I . IN fi 0 . - - - = DV,, Figure 4-28 Digital power control loop. Thanks to their requirement of desktop power packed inside thin form factors, other applications that currently have less commanding volumes, such as blade servers, offer a different value proposition and privilege size over cost. This niche has become a playground allowing a few companies to develop new and increasingly faster switchmode regulator architectures based on the more expensive but slimmer ceramic capacitors. The ultimate goal is to break the $/mQ barrier by the design of switchmode controllers and power train filters that are fast enough to respond at or above the speed of the incoming current step di/dt (say 300 A/p). Such a performance would go beyond the elimination of electrolytics and would reduce drasti- cally the number of ceramics needed on the basis of plain ESR calcula- tions. The underlying architecture would then finally defeat the established technology, with the entire regulation market being the prize. Fairchild is actively researching this field. Digital Power 105 Digital switchmode control is a fledgling architecture testing itself against the abatement of the $/mQ barrier. In the process, digital control is regularly touted as an “inherently fast” technology. As conventional digital algorithms are sequential in nature, requiring several clock cycles to exe- cute an instruction, there is nothing inherently fast about them. PWM digi- tal control is all about going beyond the CPU’s, or even the DSP’s architectures, toward hard-wired logic that can respond at the speed of the process technology. Analog techniques, which are at the same process generation level, should be at least as fast. Accordingly it is likely that at the core of future fast controllers, we will find a fast analog cell, may it be a “fast clamp,” transient suppressor, or something similar. Around this fast cell we may find all kinds of bells and whistles, some digital and some analog. What we need arefusr architectures that deal effectively with the CPU voltage regulation-the rest is optional. This Page Intentionally Left Blank 5.1 Offline Power Architectures Introduction System On u Chip (SOC) companies are claiming that the entire signal path (digital + analog + memory) and even a full GSM system-includ- ing power management-will be integrated in the next few years. How- ever, the reality is that this up-integration march, fueled by nano-scale lithography (minimum features less than 100 nm), ends up defining the product’s own technology boundaries: the higher the number of transis- tors on a chip, the lower their voltage and the more fragile their technol- ogy. At the 0.13 pm juncture, for example, the SOC processes work at voltages in the range of 1 V-2 V! At the other end of the spectrum are the power chip companies cre- ating technologies to deal with high voltages and high currents. Drawing power from the AC line down to an intermediate bus voltage requires robust devices capable of sustaining several hundred volts at several amperes. At the same time, the conversion from bus voltage to final load often requires low voltages at hundreds of amperes of current. The way power conversion requirements are met in a PC applica- tion, from line Power Fuctor Correction (PFC) to intermediate bus volt- age out of the silver box, down to the popular low voltages on the motherboard, nicely illustrates the new high-voltage and high-current silicon technologies and architectures. To describe this evolving power conversion technology, this chapter provides an application example of 107 108 Chapter 5 Offline (AC-DC) Architectures Fairchild’s single chip controller, the ML4803 PFC/PWM combo, and associated discrete transistors for the AC-DC conversion to intermediate voltage bus. Additionally, DC-DC conversion from bus to low voltage is demonstrated based on Fairchild’s FAN5092 buck converter. Future trends in PFCPWM and DC-DC converters are also discussed. Offline Control Harmonic Limits and Power Factor Correction Optimum conditions for power delivery from the AC line are achieved when the electric load, a PC for example, draws current which is in phase with the input voltage (AC line) and when such a current is undistorted (sinusoidal). To this end, IEC 6100-2-3 is the European standard specify- ing the harmonic limits of various equipment classes. For example, all per- sonal computers drawing more than 75 W must have harmonics at or below the profile demonstrated in Figure 5-1. With modern desktop PSUs drawing from 140 W to 250 W, all PCs shipped to Europe must comply. When it comes to compliance to IEC 6100-2-3, the rest of the world is fol- lowing Europe’s lead at varying paces. Figure 5-1 illustrates one aspect of the European specification. Notice that the allowance grows stricter for the higher harmonics; how- ever, these harmonics also have less energy content and are easier to filter. According to the specification, the allowed harmonic current does max out above 600 W, making it more challenging to achieve compliance at higher power. Power Factor (PF) is a global parameter speaking to the general qual- ity of the power drawn from the line. It is related to the input current Total Harmonic Distortion (THD) by the equation cos cp PF = 2 I/? (1+THD) Eq. 5-1 where cp is the phase shift between line voltage and drawn current. With no phase shift (cp = 0) and no distortion (THD = 0) it follows that PF = 1. Since the numerator Icoscpl (bars indicate module or absolute value) is bounded between zero and one and the denominator is always higher or equal to one, it follows that PF 5 1. Since IEC 6 1000-3-2 specifies the harmonic components of THD, neither THD nor PF is a sufficient measure of performance. In reality, the harmonic distortion parameter to measure and comply with (as per Offline Power Architectures 109 Figure 5-1 IEC 61000-3-2 harmonic current limits. Figure 5-1 ), and the techniques to achieve that compliance generally are called PFC. It is interesting to note that, in theory, the COST factor in the PF prod- uct can take on negative as well as positive values. Keep in mind that a negative COST value corresponds to the situation in which the load circuit is actually supplying real power to the line. In a rectifier circuit based on a diode bridge, this situation is impossible. Harmonic Limits Compliance Constraints The standard way to draw power from the AC line is via a diode bridge rectifier directly applied across the load (Figure 5-2). If the capacitor is not present, the voltage and current are both recti- fied sinusoids with no distortion, no phase shift, and PF = 1 (see Figure 5-3). In this condition, the power delivered to the load consists of a waveform of double frequency, zero minimum (meaning in Figure 5-3 the lowest part of the waveform touches the horizontal axis corresponding to zero power) and instantaneous value of P(t)=(V2/R)xsen2un=(1/2)x(V2IR)x(l -cos2~) Eq.5-2 110 Chapter 5 Offline (AC-DC) Architectures "LO, Figure 5-2 Diode bridge rectifier. where V is the amplitude of the line voltage, R is the load, and wis the line pulsation 2nJ withf= SO Hz or 60 Hz. From Eq. 5-2 the real or average power is with a time-varying zero average pulsating power of PpULs = -( 1/2) x ( V2/R) x cos2u~ Eq. 5-4 This simple example provides a model of an ideal rectification scheme as presented to the AC line. On the other hand, the scheme has no energy storage function, and the power delivered at the output of this rectifier has a double-line frequency component. Continuing in this idealized framework, a typical load actually requires constant (DC) power. Thus, an inherent requirement is a bulk energy storage element, usually realized by an electrolytic capacitor, that handles the difference in power between P(t), the input power, and PAVE, the DC output power. Adding a small capacitor C (the dashed line in Figure 5-2) to this scheme will naturally smooth the voltage across the load, reducing the rip- ple but also degrading the PFC, as the current waveform now drastically deviates from a sinusoid (see Figure 54). The scheme of Figure 5-2 (with capacitor) represents the conven- tional, non-PFC architecture used in many commercial applications prior PFC techniques are all about maintaining an input and output power match in the presence of low input harmonic current content and tightly regulated output voltage. to IEC-6 1000-3-2. Offline Power Architectures 111 "LINE, A 'LINE 0 ,t ,t PLINE Figure 5-3 Power line (PLINE = VLINE x ILINE) has double frequency. PFC Architecture The general architecture for PFC is shown in Figure 5-5. As discussed in the previous section, a PFC stage will provide a good match between line voltage and current. Assuming perfect balance (PF = 1 ), we find ourselves in the condition of Figure 5-3(a) on the AC line side. On the rectified side, the capacitor C will provide a reactive power where VcDc is the DC voltage across the capacitor, VCRIppLE is its ripple peak, and w = 2#is the line voltage pulsation cf= 50 or 60 Hz). Notice that PcR is analogous to PpuLs in the system from Figure 5-2 (no capacitor). [...]... of the elements in Figure 6 -4 2.7 to 4. 2 v m'3v 1 V DSP Core 4. 3 V Boost Boost I$ = I 3.3 V DSP 110, Bluetooth Memory rFhT LCD Contrast Boost 125VAudio ;5 Figure 6 -4 Mobile phone power management system Power Management of Wireless Computing and Communications Devices 129 Table 6-2 Semiconductor Building Block for Wireless Applications FAN2502/3/10/11/12/13 FAN25 34/ 5 FAN2 544 Dual FAN2558 Low Voltage... Global System Mobile 14. 4 Kbps Twoanda half 2.5G GPRS General Packet Radio Service 25 -40 KbpS Third 3 G EDGE Enhanced Data Rate GSM Evolution > 144 Kbpsa Third 3 G CDMA, W-CDMA Wideband Code Division Multiple Access >2 Mbps Type Description Speed The Japanese typically do not own home computers and rely increasingly on their phones to exchange text messages as well as access email and the Internet If... critical element of the power management equation but not its bottleneck The holdups are at the process and power source levels, and eliminating these bottlenecks will require new process technologies that lead to chips with reduced power dissipation and new power sources with higher power density The analog building blocks for effective power management of a wireless device in its present and future incarnations... majority of the electronics, from the baseband DSP and application MCU to the transceiver and analog interface Each of these blocks is powered by a dedicated voltage regulator The growing complexity of smart phones requires strict management of the power source This is obtained by means of a power manager” inside the baseband processor, communicating to the outside world via logic signals On the power source... mobile phone, and more in a convergent device Reaching such a level of functionality without compromising the usage model will present enormous challenges as well as opportunities for the electronics industry and in particular for power management The Wireless Landscape The wireless landscape is, and will remain for many years, very fragmented along both geographical and communications standards lines... rejection Offline Power Architectures 113 PFC and Pulse Width Modulation (PWM) Implementation A high-level block diagram of the power conversion chain, from an AC line to an intermediate voltage bus Vsus (for example, 12 V), is shown in Figure 5-6 GND *ENS V,, ‘LIMIT RC431A FAN4803 Figure 5-6 PFC and PWM chain based on FAN4803 In Figure 5-6, the control is based on a product called the FAN4803, a very compact... Figure 6-5 shows the typical block diagram of a 2G wireless handheld, in the class of the recently announced Palm i705 Figure 6-5 Block diagram of a 2G handheld computer 130 Chapter 6 Power ManaQWIEnt of Ultraportable Devices Here again each block requires a specialized power supply, but due to the absence of a DSP and of the SIM card, the power management is a bit leaner than for the case illustrated... Figure 6-6 LDO Transceiver 20 v Boost LCD Display Contrast Power management strategy for wireless handheld i' ll t 2.7 to 4. 2 V Boost 3.3v CPU T U S B Bluetooth ;5 Memory 28V 7 Transceiver l-=l- -m 3 v Power ;5 Amp"fier 20 V Display Boost LD03 Contrast 1 2 5VAudio ;5 Figure 6-7 Handheld power management system Power Management of Wireless Computing and Communications Devices 131 Here again the specific... the same standby and talk times to which the cellular customers are accustomed?) and in part cultural (will the Japanese model of connectivity illustrated at the beginning of this chapter prevail?) Future Architectures At the 3G juncture, the system complexity for cellular and smart phones is such that one DSP is not enough and an additional DSP or ASIC often is necessary to support video and audio... such breakthroughs will be as big as the entire power conversion market Power AC Adapter: Thermal and Electrical Design 119 5.2 Power AC Adapter: Thermal and Electrical Design Thermal and electrical design techniques satisfy new requirements for AC adapters Introduction: The Challenge The power management industry makes a tremendous effort to reduce the power dissipated by modern appliances, such as . as big as the entire power conversion market. Power AC Adapter: Thermal and Electrical Design 119 5.2 Power AC Adapter: Thermal and Electrical Design Thermal and electrical design. power. Thus, an inherent requirement is a bulk energy storage element, usually realized by an electrolytic capacitor, that handles the difference in power between P(t), the input power, and. Figure 5-6. GND V,, RC431A *ENS ‘LIMIT FAN4803 Figure 5-6 PFC and PWM chain based on FAN4803 In Figure 5-6, the control is based on a product called the FAN4803, a very compact