PIC18 INSTRUCTION SET 363 ; i = ArrayVar(3) // Simulate an array read movlw 2 ; Calculate Offset to 3rd Element addwf FSR, f movf INDF, w ; Get the 3rd Element movwf i ; and store it movlw -2 ; Restore FSR to point to first element addwf FSR, f This code has to first add 2 to the current address in the FSR, followed by loading and storing the third element and then returning the index pointer to the first element in the array. Now, compare this to the same code for the PIC18 in which FSR0 (which means that the PLUSW0 register will be used to access the data) points to the start of ArrayVar. ; i = ArrayVar(3) // Simulate an array read movlw 2 ; Want Offset to the 3rd Element movff PLUSW0, i ; Move Contents of ArrayVar(3) into i The PREINC and POSTDEC INDF registers can be used for popping and pushing, respectively, data onto a stack pointed to by an FSR register. The POSTDEC INDF reg- ister is used for the push operation because it will allow the access of pushed data using the PLUSW INDF register as shown in the previous example. Using FSR0 for the stack, the byte push function could be as simple as: BytePush: ; Push the contents of “i” onto the stack movff i, POSTDEC0 return and the byte pop could be: BytePop: ; Pop the top of the stack movff PREINC0, i return The PLUSW INDF register comes in useful for high level functions in which data has been pushed onto the stack to implement temporary variables. In the example below, I have specified a function that uses a data stack and with the parameters and local vari- ables (the same thing) being pushed onto a stack implemented with FSR0: ; int StackDemo(char i, char j) // “i” is stack top, “j” is one less ; { ; char k = 0; // “k” is at two less than stack top movlw 0 ; Initialize “k” to zero movwf POSTDEC, 0 ; ; i = j + k; // Perform a basic calculation movlw 2 ; Get offset to “j” Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com 364 USING THE PIC MCU INSTRUCTION SET movff Temp, PLUSW0 ; Store value in “Temp” movlw 1 ; Get offset to “k” movf PLUSW0 addwf Temp, f, 0 ; Add “k” to “j” in “Temp” movlw 3 ; Get offset to “i” movff PLUSW0, Temp ; Store result While this code may look very complex, it is actually simple and, once you are com- fortable with it, very easy to implement. This capability is also critical for efficient implementation of compilers that implement local variables as shown here. DATA PROCESSING INSTRUCTIONS The PIC18 has some added flexibility and conventional capabilities compared to the other PIC microcontroller processors. As you look through the PIC18 instruction set, you will see that the additions and modifications to its instruction set make it more similar to that of other processors while retaining the PIC18’s ability to create very efficient code. The most significant addition to the PIC18’s data processing instructions is the subfwb (Fig. 7.49) instruction. This instruction carries out a subtract operation with borrow in the order most people are familiar with if they have worked with other proces- sors. Instead of the typical PIC microcontroller subtraction instruction: Result = (Source Value) – WREG [- !C] the subfwb instruction executes as: Result = WREG – (Source Value) - !C Program Memory Register Space Register Address Bus PC Program Counter Stack ALU Fast Stack InstructionRegister/ Decode Second Instruction Register STATUS WREG BSR FSR File Registers Instruction Bit Pattern: 12345678 12345678 Instruction Operation: Destination = WREG - Reg - !C Flags Affected: N, OV, C, DC, Z Instruction Cycles: 1 Notes: This instructionbehaves like a “Traditional” Subtract and is different from the “Standard” subtraction Instructio ns Available in the other PICmi cro architectures 010101da ffffffff Figure 7.49 The subfwb instruction provides the expected subtract operation instead of the addition of the negated value of WREG used by the other subtract instructions. Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com PIC18 INSTRUCTION SET 365 This instruction frees you from the need of thinking backwards when subtraction instructions are used in an application. To use the subfwb instruction, WREG is loaded with the value to be subtracted from (the subtend) and the value to take away (the sub- tractor) is specified in the instruction. This means that if you have the statement: A = B – C the values of the expression can be loaded in the same left to right order as the PIC micro- controller instructions and use the sequence: bcf STATUS, C, 0 movf B, w, 0 subfwb C, w, 0 movwf A, 0 This is the same order as would be used in most other processors. Note that I reset the carry flag before the instruction sequence to avoid any possibilities of the carry being reset unexpectedly and taking away an extra 1, which will be very hard to find in application code. A PIC18 16-bit subtraction operation could be: bcf STATUS, C movf B, w, 0 subfwb C, w, 0 movwf A, 0 movf B + 1, w, 0 subfwb C + 1, w, 0 movwf A + 1, 0 Or if you want to save on the instruction used to clear the carry flag at the start of the sequence: movf C, w, 0 subwf B, w, 0 movwf A, 0 movf B + 1, w, 0 subfwb C + 1, w, 0 movwf A + 1, 0 Another difference between the PIC18 and the other PIC microcontroller processors is the inclusion of the negf (Fig. 7.50) instruction, which can negate any register in the PIC18’s register space. The single instruction cycle multiply instructions multiply the contents of WREG against the contents of another register (mulfw) or a constant (mullw) and store the 16-bit product in the PRODH:PRODL register combination (Fig. 7.51). These instruc- tions are very well behaved and will work for 2’s complement numbers and can pro- vide you with some basic digital signal processing (DSP) capabilities in the PIC18. Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com 366 USING THE PIC MCU INSTRUCTION SET EXECUTION CHANGE INSTRUCTIONS The PIC18’s execution change instructions, upon first glance, should be very familiar to you if you are familiar with the other PIC microcontroller families. The PIC18 has the btfsc, btfss, goto, and call of the low-end and mid-range PIC microcontrollers along with the compare and skip on equals (cpfseq), greater than (cpfsgt), and less than (cpfslt). The PIC18 also has the enhanced increment and skip on result not equal to zero (infsnz and dcfsnz). Along with these similarities, the PIC18 has four new features that you should be aware of (and remember their availability) when you are devel- oping applications for it. The first feature that you should be aware of is the goto and call instructions, which can directly any address in the program memory space. As shown in Fig. 7.52, these instructions are built from two 16-bit words and contain the entire 20 word address bits to allow you to jump anywhere in program memory. Program Memory Register Space Register Address Bus PC Program Counter Stack ALU Fast Stack Instruction Register/ Decode Second Instruction Register STATUS WREG BSR FSR File Registers Instruction Bit Pattern: 12345678 12345678 Instruction Operation: Reg = (Reg ^ 0x0FF) + 1; Flags Affected: C, DC, N, OV, Z Instruction Cycles: 1 Notes: All Flags are Affected by this Instruction 0110110a ffffffff Figure 7.50 The negf instruction will two’s complement ny register in the PIC18 register space. PRODH:PRODL 8x8 Multiplier WREG Parm (Register for mulwf Constant for mullw) Figure 7.51 The two single instruction cycle 8 by 8 multiplication instructions store their result in PRODH:PRODL. Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com PIC18 INSTRUCTION SET 367 The call instruction (as well as the corresponding return) instruction has the capa- bility, when a 1 is specified as the s bit at the end of the instruction, of saving the con- text registers WREG, BRS, and STATUS in shadow registers of the fast stack, which are retrieved by the return instruction by specifying a 1 as well. The issue that you should be aware of for the context save is that you can only save one set of values on the fast stack and the context values of the mainline are always saved when an interrupt is acknowledged. This limits the usability of the context register save to applications that only have a single deep call and no interrupts. For your first PIC18 applications, I would recommend that you use the instruction set’s single word instructions only. The only time you should be using the goto or call instructions is if you have to access a memory location outside the range of the relative branches. This range is –512 to +511 instruction addresses for the bra (branch always) and rcall (relative call) instructions and –64 to +63 instruction addresses for the con- ditional branch instructions that I will discuss below. The rcall instruction informa- tion is shown in Fig. 7.53. Along with using the single word execution change instructions, I also recommend that you be careful when using the $ directive and branching relative to it. When the assembler is calculating addresses, it works on a byte basis, not a word basis as it does for other PIC microcontrollers. This means that you must multiply the number of instruc- tions by 2 to get the correct address. Consider the simple delay loop: movlw 47 ; Loop 47x3 instruction cycles decfsz WREG, f, 0 bra $ - 1 Program Memory Register Space Register Address Bus PC Program Counter Stack ALU Fast Stack InstructionRegister/ Decode Second Instruction Register STATUS WREG BSR FSR Instruction Bit Pattern: 12345678 12345678 Instruction Operation: Call: if (s == 1) Push Context Registers; Push Next Address; Jump to Address Goto: Jump to Address Flags Affected: None Instruction Cycles: 2 Notes: “Call” and “Goto” areTwo Wo rd Instructions. Each Instruction can Access ANY Progr am Memory Location in the PICmicro. “Call” can optionally do the “Fast Stack” Context Register Save call 1110110s nnnnnnnn 12345678 12345678 1111nnnn nnnnnnnn 12345678 12345678goto 11101111 nnnnnnnn 12345678 12345678 1111nnnn nnnnnnnn File Registers Figure 7.52 The PIC18 call and goto instructions provide the capability of accessing any address in program memory without the need of updating the PCLATH or PCLATU registers. Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com 368 USING THE PIC MCU INSTRUCTION SET If you were to enter the code into the PIC18InsTemplt.asm project and build it, you would get a warning indicating that the instruction cannot start at an odd address. To fix the problem, you have to multiply the offset by 2, producing the code: movlw 47 ; Loop 47x3 instruction cycles decfsz WREG, f, 0 bra $ - (1 * 2) which will build cleanly and you can simulate to see that it actually takes 141 (47 times 3) instructions. If you want to avoid this difference between the PIC18 and the other devices, I would recommend that you always use labels and never use rel- ative addressing. Above, I indicated that there was a one word goto instruction called bra (branch always). This instruction type (shown in Fig. 7.54) changes the program counter accord- ing to the 2’s complement offset provided in the instruction according to the formula: PCnew = PCcurrent + 2 + Offset where PCcurrent is the current address of the executing branch instruction. The 2 added to PCcurrent results in the address after the current one. Offset is the 2’s complement value, which is added or subtracted (if the Offset is negative) from the sum of PCcurrent and 2. The MPASM assembler computes the correct offset for you when the destination of a branch instruction is a label. MPASM computes the 2’s complement offset using the formula: Offset = Destination – (Current Address) Program Memory Register Space Register Address Bus PC Program Counter Stack ALU Fast Stack InstructionRegister/ Decode Second Instruction Register STATUS WREG BSR FSR File Registers Instruction Bit Pattern: Instruction Operation: Push Next Address; PC = PC + 2 + 2's Complement “n”; Flags Affected: None Instruction Cycles: 2 Notes: Rcall 2’s Complement Offset is Added to the Address of the Next Instruction. Note, the 2’s Complement Offset MUST be even 11011nnn nnnnnnnn Figure 7.53 The rcall instruction allows accessing subroutines that start –64 to +63 instructions from the current program counter location. Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com PIC18 INSTRUCTION SET 369 If the destination is outside the range of the instruction it is flagged as an error by the MPASM assembler. Along with the nonconditional branch, there are 8 conditional branch instructions available in the PIC18 and they are shown in Fig. 7.54. They are branch on zero flag set (bz), branch on zero flag reset (bnz), branch on carry flag set (bc), branch on carry flag reset (bnc), branch on negative flag set (bn), branch on negative flag reset (bnn), branch on overflow flag set (bov), and branch on overflow flag reset (bnov). These instructions are equivalent to the branch on condition instructions found in other processors. These instructions behave similarly to the bra instruction except that they have 8 bits for the offset address (to the bra instruction’s 11). This gives the instructions the ability to change the program counter by –64 to +63 instructions. The last new feature of the PIC18 architecture that is different from the other archi- tectures is the fast stack, in which WREG, STATUS, and BSR registers are saved non- conditionally upon the interrupt acknowledge and vector jump and conditionally during a subroutine call instruction. These registers can be optionally restored after a return or retfie instruction. Tables PIC18 tables are executed as: TableRead: movwf TableOff, 0 bcf STATUS, C, 0 ; First Calculate if past first 256 rlcf TableOff, w, 0 ; addresses and by how much Program Memory Register Space PC Program Counter Stack ALU Fast Stack Instruction Register/ Decode Second Instruction Register STATUS WREG BSR FSR File Registers Instruction Bit Pattern: 12345678 12345678 Instruction Operation: BC/BNC: Branch on Carry Flag BN/BNN: Branch on “N” Flag BOV/BNOV: Branch on “OV” Flag BZ/BNZ: Branch on Zero Flag BRA: Branch Allways Flags Affected: None Instruction Cycl es: 2 if Branch Taken 1 otherwise Notes: Offset “n” is a Two’s Complement Number BC 11000010 nnnnnnnn 12345678 12345678BNC 11100011 nnnnnnnn 12345678 12345678BN 11100110 nnnnnnnn 12345678 12345678BNN 11100011 nnnnnnnn 12345678 12345678BOV 11100100 nnnnnnnn 12345678 12345678BNOV 11100101 nnnnnnnn 12345678 12345678BZ 11100000 nnnnnnnn 12345678 12345678BNZ 11100001 nnnnnnnn 12345678 12345678BRA 11010nnn nnnnnnnn Figure 7.54 The branch instruction can access addresses –512 to +511 instructions from the current program counter location. Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com 370 USING THE PIC MCU INSTRUCTION SET addlw Table & 0xFF movf STATUS, w, 0 andlw 1 btfsc TableOff, 7, 0 addlw 1 addlw (Table >> 8) & 0xFF ; Add Offset to start of table to movwf PCLATH, 0 ; PCLATH movf STATUS, w, 0 ; If in Next Page, increment PCLATU andlw 1 addlw UPPER Table movwf PCLATU, 0 rlcf TableOff, w, 0 ; Calculate offset within 256 address addlw LOW Table movwf PCL, 0 Table: dt If the purpose of the computed goto is to return a byte value (using retlw), then I would suggest taking advantage of the 16-bit instruction word, store 2 bytes in an instruction word, and use the table read instructions to read back two values. This is some- what more efficient in terms of coding and requires approximately the same number of instructions and instruction cycles. A computed byte table read (which allows compressed data) consists of the follow- ing subroutine. TableRead: movwf TableOff movlw LOW Table ; Calculate address addwf TableOff, w, 0 movwf TBLPTRL, 0 movlw (Table >> 8) & 0xFF btfsc STATUS, C, 0 addlw 1 movwf TBLPTRH, 0 movlw UPPER Table btfsc STATUS, C, 0 addlw 1 movwf TBLPTRU, 0 TBLRD * ; Read byte at address movf TABLAT, w, 0 ; Return the byte return Table: db Interrupts When I show a basic interrupt handler for the mid-range PIC microcon- trollers, along with the w and STATUS registers, I also include saving the contents of the FSR and the PCLATH registers. This is not required in the PIC18 because of the Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com PIC18 INSTRUCTION SET 371 multiple FSR registers available and the ability to jump anywhere within the applica- tion without using the PCLATH or PCLATU registers. If an FSR register is required within an interrupt handler, chances are it can be reserved for this use within the appli- cation when resources are allocated. When a hardware interrupt request is acknowledged, the current WREG, STATUS, and BSR are saved in the fast stack. The PCLATH (and PCLATU) registers should not have to be saved in the interrupt handler unless a traditional table read (i.e., using a com- puted goto) is implemented instead of a table read using the built-in instructions (and shown in the previous section). The goto and branch instructions update the program counter without accessing the PCLATH and PCLATU registers. These conditions will allow a PIC18 interrupt handler with context saving to be as simple as: org 8 Int ; #### - Execute Interrupt Handler Code retfie 1 so long as nested interrupts are not allowed and subroutine calls do not use the fast stack. PROCESSOR CONTROL INSTRUCTIONS The PIC18Cxx has the same processor instructions as the other PIC microcontrollers, but there is one instruction enhancement that I would like to bring to your attention. When designing the PIC18Cxx, the Microchip designers did something I’ve wanted for years: they created a nop instruction (Fig. 7.55) that has two bit patterns, all bits set and all Program Memory Register Space Register Address Bus PC Program Counter Stack ALU Fast Stack Instruction Register/ Decode Second Instruction Register STATUS WREG BSR FSR File Registers Instruction Bit Pattern: 12345678 12345678 Instruction Operation: Flags Affected: None Instruction Cycles: 1 Notes:There are two bit patterns for this instruction 00000000 00000000 12345678 12345678 11111111 11111111 or: Figure 7.55 The nop instruction is coded as either all bits set or all bits reset. Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com 372 USING THE PIC MCU INSTRUCTION SET bits reset. The profoundness of this instruction and what can be done with it will prob- ably not be immediately obvious to you. In the PIC18, just the patch space instructions that are to be modified are changed and no space is required for jumping around instructions. For the same example in the PIC18, the patch space would be: dw 0x0FFFF ; nop dw 0x0FFFF ; nop dw 0x0FFFF ; nop dw 0x0FFFF ; nop dw 0x0FFFF ; nop dw 0x0FFFF ; nop To add three instructions to the patch space, just the required changes for the three instructions are made: movf B, w, 0 ; Formerly “dw 0x0FFFF” addwf C, w, 0 ; Formerly “dw 0x0FFFF” movwf A, 0 ; Formerly “dw 0x0FFFF” dw 0x0FFFF ; nop dw 0x0FFFF ; nop dw 0x0FFFF ; nop Note that to add three instructions in this case, only three instructions of the patch space are modified and there is no need for a goto instruction to jump around the unpro- grammed addresses as you would for the low-end or mid-range PIC microcontroller architectures. Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com [...]... in the PIC microcontroller) For most of these programming tips, the person who came up with them not only had the need to do them but also understood the PIC microcontroller architecture and instruction set well enough to look for better ways to implement the functions than the most obvious At the risk of sounding Zen, I want to say that the PIC microcontroller is best programmed when you are in the. .. when programming other devices In this section I want to discuss the different memory “spaces” in the PIC microcontroller, what is stored in them, and how they are accessed The most familiar memory space to you is probably the instruction program memory As I said earlier in this book, the program memory is the width of the instruction word The maximum “depth” of the memory is based on the word size and. .. Load the w register with the second parameter (which is the value to be taken away from the first) 2 Subtract the contents of the w register from the first parameter and store the result in the w register 3 Store the contents of the w register in the destination In PIC microcontroller assembly code, this is movf subwf movwf Parm2, w Parm1, w Destination As with the addition operation, the movf and subwf... the word size and can have the instruction word size minus one for addressing for the low-end and mid-range PIC microcontrollers The PIC1 8 is a bit different because it expands on the concepts used by the other architectures, allowing you to have a much larger program space To figure out the maximum depth of program memory in the low-end and mid-range PIC microcontrollers, the formula Maximum program... or sublw, respectively, if either Parm1 or Parm2 is a constant The PIC microcontroller s instructions contrasts with those of the 8051 and other microcontroller architectures, in which the subtract instruction takes away the parameter value from the contents of the accumulator As I have indicated elsewhere, the PIC microcontroller subtract instruction actually works as PIC microcontroller subtract =... as one-third the clock cycles and instructions that would be required in other microcontrollers This level of optimization is not a function of learning the instruction set and some rules Instead, it is a result of thoroughly understanding how the PIC microcontroller works and being able to visualize the best path for data within the processor and have a feel for the data flowing through the chip 373... and it has remained very constant over the years;I first started creating assembly-language templates for IBM PC assembly-language programming, and this practice has served me well with the PIC microcontroller as well as other devices The title and _version at the top of the file show what the application does so that I can scan the files very quickly instead of going by what the file name indicates The. .. detail elsewhere in the book The size of the page in the various PIC microcontroller architecture families is based on the maximum number of bits that could be put into an instruction for the address In the low-end PIC microcontroller, a maximum of 9 bits are available in the goto instruction that is used to address a page of 512 instructions In the mid-range PIC microcontroller, the number of bits... to be Pressed The $ character returns a constant integer value that is the address of the instruction where it is located The goto $ - 1 instruction loads the address that is the address of the goto $ - 1 instruction minus 1 Further confusing the issue is how the PIC1 8 operates The PIC1 8 microcontroller processor behaves more like a traditional processor and has absolute address jumps and relative address... that the preceding example code will do, but it is specific to one address in the PIC microcontroller By using the goto $ - 1 instruction, the code can be “cut and pasted” anywhere within the application or used in other applications Letting the assembler generate the addresses for you is accomplished in one of two ways The first is the Label, which is placed in the first column of the source code and . in the PIC micro- controller). For most of these programming tips, the person who came up with them not only had the need to do them but also understood the PIC microcontroller architecture and. families. The PIC1 8 has the btfsc, btfss, goto, and call of the low-end and mid-range PIC microcontrollers along with the compare and skip on equals (cpfseq), greater than (cpfsgt), and less than. between the PIC1 8 and the other PIC microcontroller processors is the inclusion of the negf (Fig. 7.50) instruction, which can negate any register in the PIC1 8’s register space. The single instruction