ELEC-2005 Electronics in High Energy Physics Winter Term: Introduction to Electronics in HEP Field Programmable Gate Arrays Part 1 Stefan Haas stefan.haas@cern.ch CERN Technical Training 2005 Stefan Haas, 1 F eb. 2005 ELEC-2005 2 Part 2 • VHDL – Introduction – Examples • Design Flow – Entry Methods – Simulation – Synthesis – Place & Route • IP Cores • CERN Tools & Support Part 1 • Programmable Logic • CPLD • FPGA – Architecture – Examples – Features – Vendors and Devices coffee break Outline Programmable Logic Stefan Haas, 1 F eb. 2005 ELEC-2005 4 Programmable Logic • Programmable digital integrated circuit • Standard off-the-shelf parts • Desired functionality is implemented by configuring on-chip logic blocks and interconnections • Advantages (compared to an ASIC): – Low development costs – Short development cycle – Device can (usually) be reprogrammed • Types of programmable logic: – Complex PLDs (CPLD) – Field programmable Gate Arrays (FPGA) CPLD Architecture and Examples Stefan Haas, 1 F eb. 2005 ELEC-2005 6 PLD - Sum of Products A B C CBACBAf ••+••= 1 CBABAf ••+•= 2 AND plane Programmable AND array followed by fixed fan-in OR gates Programmable switch or fuse Stefan Haas, 1 F eb. 2005 ELEC-2005 7 PLD - Macrocell Can implement combinational or sequential logic A B C Flip-flop Select Enable D Q Clock AND plane MUX 1 f Stefan Haas, 1 F eb. 2005 ELEC-2005 8 CPLD Structure Integration of several PLD blocks with a programmable interconnect on a single chip PLD Block PLD Block PLD Block PLD Block Interconnection Matrix Interconnection Matrix I/O Block I/O Block I/O Block I/O Block PLD Block PLD Block PLD Block PLD Block I/O Block I/O Block I/O Block I/O Block • • • Interconnection Matrix Interconnection Matrix • • • • • • • • • Stefan Haas, 1 F eb. 2005 ELEC-2005 9 CPLD Example - Altera MAX7000 EPM7000 Series Block Diagram Stefan Haas, 1 F eb. 2005 ELEC-2005 10 CPLD Example - Altera MAX7000 EPM7000 Series Device Macrocell [...]... needs to be configured at power-on • Flash Erasable Programmable ROM (Flash) – each switch is a floating -gate transistor that can be turned off by injecting charge onto its gate FPGA itself holds the program – reprogrammable, even in-circuit • Fusible Links (“Antifuse”) – Forms a forms a low resistance path when electrically programmed – one-time programmable in special programming machine – radiation...FPGA Architecture FPGA - Generic Structure FPGA building blocks: Logic block Interconnection switches • I/O I/O I/O Programmable logic blocks Implement combinatorial and sequential logic • Programmable interconnect Wires to connect inputs and outputs to logic blocks • Programmable I/O blocks Special logic blocks at the periphery of device for external connections I/O Stefan Haas, 1 F ELEC-2005... LE LE LE ELEC-2005 LE LE LE LE 17 Switch Matrix Operation Before Programming • • • After Programming 6 pass transistors per switch matrix interconnect point Pass transistors act as programmable switches Pass transistor gates are driven by configuration memory cells Stefan Haas, 1 F ELEC-2005 18 Special Features • Clock management – PLL,DLL – Eliminate clock skew between external clock input and on-chip... LUT LUT Z LUT implementation A B Z C D Truth-table Stefan Haas, 1 F Gate implementation ELEC-2005 15 LUT Implementation • Example: 3-input LUT • Based on multiplexers (pass transistors) • LUT entries stored in configuration memory cells X1 X2 0/1 0/1 0/1 0/1 F 0/1 0/1 0/1 Configuration memory cells 0/1 X3 Stefan Haas, 1 F ELEC-2005 16 Programmable Interconnect • Interconnect hierarchy (not shown) – Fast . power-on • Flash Erasable Programmable ROM (Flash) – each switch is a floating -gate transistor that can be turned off by injecting charge onto its gate. FPGA itself holds the program – reprogrammable, even. development cycle – Device can (usually) be reprogrammed • Types of programmable logic: – Complex PLDs (CPLD) – Field programmable Gate Arrays (FPGA) CPLD Architecture and Examples Stefan Haas, 1 F eb ELEC-2005 Electronics in High Energy Physics Winter Term: Introduction to Electronics in HEP Field Programmable Gate Arrays Part 1 Stefan Haas stefan.haas@cern.ch CERN Technical Training 2005 Stefan Haas,