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Bài giới thiệu về chip ADC8052
TS80C32X2 TS87C52X2 TS80C52X2 8-bit Microcontroller Kbytes ROM/OTP, ROMless Description TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source , 4-level interrupt system, an on-chip oscilator and three timer/counters In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism The fully static design of the TS80C52X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data The TS80C52X2 has software-selectable modes of reduced activity for further reduction in power consumption In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating In the power-down mode the RAM is saved and all other functions are inoperative Features q 80C52 Compatible q Interrupt Structure with • 8051 pin and instruction compatible • Interrupt sources, • Four 8-bit I/O ports • level priority interrupt system • Three 16-bit timer/counters q Full duplex Enhanced UART • 256 bytes scratchpad RAM q • Framing error detection High-Speed Architecture • Automatic address recognition • 40 MHz @ 5V, 30MHz @ 3V • X2 Speed Improvement capability (6 clocks/ machine cycle) q Low EMI (inhibit ALE) q Power Control modes • Idle mode 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V) • Power-down mode • Power-off Flag q Dual Data Pointer q On-chip ROM/EPROM (8Kbytes) q Once mode (On-chip Emulation) q Programmable Clock Out and Up/Down Timer/ Counter q Power supply: 4.5-5.5V, 2.7-5.5V q Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC) q Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint), CQPJ44 (window), CDIL40 (window) q Asynchronous port reset Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 Table Memory size ROM (bytes) EPROM (bytes) TOTAL RAM (bytes) 8k 0 8k 256 256 256 TS80C32X2 TS80C52X2 TS87C52X2 (3) (3) (1) XTAL1 EUART XTAL2 ALE/ PROG RAM 256x8 C51 CORE PSEN ROM /EPROM 8Kx8 T2 T2EX Vss Vcc TxD RxD Block Diagram (1) Timer2 IB-bus CPU EA/VPP Timer Timer (3) INT Ctrl Parallel I/O Ports & Ext Bus Port Port Port Port P3 P2 P1 (3) (3) P0 T1 T0 RESET (3) (3) INT1 WR (3) INT0 RD (1): Alternate function of Port (3): Alternate function of Port Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 SFR Mapping The Special Function Registers (SFRs) of the TS80C52X2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • Power and clock control registers: PCON • Interrupt system registers: IE, IP, IPH • Others: AUXR, CKCON Table All SFRs with their address and their reset value Bit addressable 0/8 Non Bit addressable 1/9 2/A 3/B 4/C 5/D 6/E 7/F F8h F0h FFh B 0000 0000 F7h E8h E0h EFh ACC 0000 0000 E7h D8h DFh D0h PSW 0000 0000 C8h T2CON 0000 0000 D7h T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CFh C0h C7h B8h IP XX00 0000 SADEN 0000 0000 B0h P3 1111 1111 A8h IE 0X00 0000 A0h P2 1111 1111 98h SCON 0000 0000 90h P1 1111 1111 88h TCON 0000 0000 TMOD 0000 0000 TL0 0000 0000 TL1 0000 0000 80h P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8 1/9 2/A 3/B BFh IPH XX00 0000 SADDR 0000 0000 B7h AFh AUXR1 XXXX XXX0 A7h SBUF XXXX XXXX 9Fh 97h TH0 0000 0000 5/D AUXR XXXXXXX0 6/E CKCON XXXX XXX0 8Fh PCON 00X1 0000 4/C TH1 0000 0000 87h 7/F reserved Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 Pin Configuration P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.0/AD0 VSS1/NIC* VCC P1.0/T2 37 P0.6/AD6 RST 10 36 P0.7/AD7 P3.0/RxD 35 34 33 EA/VPP P3.1/TxD 11 12 13 P3.2/INT0 P3.3/INT1 14 15 32 31 PSEN P3.4/T0 P3.5/T1 16 30 P2.6/A14 17 29 P2.5/A13 NIC* P2.4 / A12 P2.3 / A11 P2.2 / A10 PLCC/CQPJ 44 P0.5/AD5 NIC* ALE/PROG P2.7/A15 18 19 20 21 22 23 24 25 26 27 28 P2.1 / A9 P2.0 / A8 P2.3/A11 P2.4/A12 23 22 21 P2.2/A10 24 P1.7 P2.1/A9 25 17 18 19 20 P0.4/AD4 NIC* P2.0/A8 16 39 38 VSS 26 44 43 42 41 40 XTAL1 14 15 P3.6/WR CDIL40 29 28 27 P0.3/AD3 PDIL/ P1.1/T2EX EA/VPP ALE/PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 11 12 13 P1.4 VSS 31 30 10 P1.6 P0.6 / A6 P0.2/AD2 XTAL1 P0.7 / A7 P0.1/AD1 P3.7/RD XTAL2 32 P1.5 P0.0/AD0 P3.5/T1 P3.6/WR P0.5 / A5 VCC P3.4/T0 P0.3 / A3 P0.4 / A4 VSS1/NIC* P3.2/INT0 P3.3/INT1 36 35 34 33 P1.0/T2 P3.0/RxD P3.1/TxD P1.1/T2EX P1.7 RST P0.1 / A1 P0.2 / A2 P1.2 P1.6 37 P1.3 P1.4 P1.5 P1.2 P0.0 / A0 P1.3 VCC 39 38 XTAL2 40 P1.4 P3.7/RD P1.0 / T2 P1.1 / T2EX P1.2 P1.3 44 43 42 41 40 39 38 37 36 35 34 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 33 32 P0.4/AD4 31 P0.6/AD6 30 P0.7/AD7 29 28 27 EA/VPP PSEN 26 25 10 24 P2.6/A14 11 23 P2.5/A13 PQFP44 VQFP44 P0.5/AD5 NIC* ALE/PROG P2.7/A15 P2.3/A11 P2.4/A12 P2.2/A10 P2.1/A9 NIC* P2.0/A8 VSS XTAL1 XTAL2 P3.7/RD P3.6/WR 12 13 14 15 16 17 18 19 20 21 22 *NIC: No Internal Connection Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 Table Pin Description for 40/44 pin packages MNEMONIC PIN NUMBER TYPE NAME AND FUNCTION 16 39 I I 44 38 I 39-32 43-36 37-30 I/O P1.0-P1.7 1-8 2-9 40-44 1-3 I/O P2.0-P2.7 21-28 24-31 40 41 18-25 I/O I I/O P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O 10 11 12 11 13 14 I O I Ground: 0V reference Optional Ground: Contact the Sales Office for ground connection Power Supply: This is the power supply voltage for normal, idle and powerdown operation Port 0: Port is an open-drain, bidirectional I/O port Port pins that have 1s written to them float and can be used as high impedance inputs.Port pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption Port is also the multiplexed low-order address and data bus during access to external program and data memory In this application, it uses strong internal pull-up when emitting 1s Port also inputs the code bytes during EPROM programming External pull-ups are required during program verification during which P0 outputs the code bytes Port 1: Port is an 8-bit bidirectional I/O port with internal pull-ups Port pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs As inputs, Port pins that are externally pulled low will source current because of the internal pull-ups Port also receives the low-order address byte during memory programming and verification Alternate functions for Port include: T2 (P1.0): Timer/Counter external count input/Clockout T2EX (P1.1): Timer/Counter Reload/Capture/Direction Control Port 2: Port is an 8-bit bidirectional I/O port with internal pull-ups Port pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs As inputs, Port pins that are externally pulled low will source current because of the internal pull-ups Port emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port emits the contents of the P2 SFR Some Port pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.4 Port 3: Port is an 8-bit bidirectional I/O port with internal pull-ups Port pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs As inputs, Port pins that are externally pulled low will source current because of the internal pull-ups Port also serves the special features of the 80C51 family, as listed below RXD (P3.0): Serial input port TXD (P3.1): Serial output port 13 14 15 16 17 15 16 17 18 19 10 10 11 12 13 I I I O O I DIL LCC VQFP 1.4 VSS Vss1 20 22 VCC 40 P0.0-P0.7 Reset Rev.D - 16 November, 2000 INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer external input T1 (P3.5): Timer external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC TS80C32X2 TS87C52X2 TS80C52X2 Table Pin Description for 40/44 pin packages TYPE NAME AND FUNCTION ALE/PROG 30 PIN NUMBER 33 27 O (I) PSEN 29 32 26 O EA/VPP 31 35 29 I Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking Note that one ALE pulse is skipped during each access to external data memory This pin is also the program pulse input (PROG) during EPROM programming ALE can be disabled by setting SFR’s AUXR.0 bit With this bit set, ALE will be inactive during internal fetches Program Store ENable: The read strobe to external program memory When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory PSEN is not activated during fetches from internal program memory External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD) If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless devices This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming If security level is programmed, EA will be internally latched on Reset XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier MNEMONIC Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 TS80C52X2 Enhanced Features In comparison to the original 80C52, the TS80C52X2 implements some new features, which are: • The X2 option • The Dual Data Pointer • The level interrupt priority system • The power-off flag • The ONCE mode • The ALE disabling • Some enhanced features are also located in the UART and the timer 6.1 X2 Feature The TS80C52X2 core needs only clock periods per machine cycle This feature called ”X2” provides the following advantages: q Divide frequency crystals by (cheaper crystals) while keeping same CPU power q Save power consumption while keeping same CPU power (oscillator power saving) q Save power consumption by dividing dynamically operating frequency by in operating and idle modes q Increase CPU power by while keeping same crystal frequency In order to keep the original C51 compatibility, a divider by is inserted between the XTAL1 signal and the main clock input of the core (phase generator) This divider may be disabled by software 6.1.1 Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals This allows any cyclic ratio to be accepted on XTAL1 input In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60% Figure shows the clock generation block diagram X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode Figure shows the mode switching waveforms XTAL1 FXTAL XTAL1:2 state machine: clock cycles CPU control FOSC X2 CKCON reg Figure Clock Generation Diagram Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 XTAL1 XTAL1:2 X2 bit CPU clock STD Mode X2 Mode STD Mode Figure Mode Switching Waveforms The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to clock cycles and vice versa At reset, the standard speed is activated (STD mode) Setting this bit activates the X2 feature (X2 mode) CAUTION In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers) will have their time reference divided by two For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms UART with 4800 baud rate will have 9600 baud rate Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 Table CKCON Register CKCON - Clock Control Register (8Fh) - - - - - - - X2 Bit Number Bit Mnemonic - Reserved The value read from this bit is indeterminate Do not set this bit - Reserved The value read from this bit is indeterminate Do not set this bit - Reserved The value read from this bit is indeterminate Do not set this bit - Reserved The value read from this bit is indeterminate Do not set this bit - Reserved The value read from this bit is indeterminate Do not set this bit - Reserved The value read from this bit is indeterminate Do not set this bit - Reserved The value read from this bit is indeterminate Do not set this bit X2 Description CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2) Set to select clock periods per machine cycle (X2 mode, FOSC=FXTAL) Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com) Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 6.2 Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways The dual DPTR structure is a way by which the chip will specify the address of an external data memory location There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3) External Data Memory DPS AUXR1(A2H) DPTR1 DPTR0 DPH(83H) DPL(82H) Figure Use of Dual Pointer 10 Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 Symbol ICC idle Parameter Min Typ Power Supply Current Maximum values, X1 mode: (7) Max 0.15 Freq (MHz) + 0.2 @12MHz @16MHz 2.6 Unit mA Test Conditions VCC = 3.3 V(2) NOTES ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = ns (see Figure 17.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port = VCC ICC would be slightly higher if a crystal oscillator used Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 N.C; Port = VCC; EA = RST = VSS (see Figure 15.) Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT = VCC; XTAL2 NC.; RST = VSS (see Figure 16.) Capacitance loading on Ports and may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports and The noise is due to external bus capacitance discharging into the Port and Port pins when these pins make to transitions during bus operation In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V A Schmitt Trigger use is not necessary Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature and 5V Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions For other values, please contact your sales office Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = ns (see Figure 17.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port = VCC; RST = VSS The internal ROM runs the code 80 FE (label: SJMP label) ICC would be slightly higher if a crystal oscillator is used Measurements are made with OTP products when possible, which is the worst case VCC ICC VCC P0 VCC RST (NC) CLOCK SIGNAL VCC EA XTAL2 XTAL1 VSS All other pins are disconnected Figure 13 ICC Test Condition, under reset 42 Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST EA XTAL2 XTAL1 (NC) CLOCK SIGNAL All other pins are disconnected VSS Figure 14 Operating ICC Test Condition VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST EA XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected Figure 15 ICC Test Condition, Idle Mode VCC ICC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) VCC EA XTAL2 XTAL1 VSS All other pins are disconnected Figure 16 ICC Test Condition, Power-Down Mode VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns 0.7VCC 0.2VCC-0.1 Figure 17 Clock Signal Waveform for ICC Tests in Active and Idle Modes Rev.D - 16 November, 2000 43 TS80C32X2 TS87C52X2 TS80C52X2 10.5 AC Parameters 10.5.1 Explanation of the AC Symbols Each timing symbol has characters The first character is always a “T” (stands for time) The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for Example:TAVLL = Time for Address Valid to ALE Low TLLPL = Time for ALE Low to PSEN Low TA TA TA TA = = = = to +70°C (commercial temperature range); VSS = -40°C to +85°C (industrial temperature range); VSS to +70°C (commercial temperature range); VSS = -40°C to +85°C (industrial temperature range); VSS V; VCC = V ± 10%; -M and -V ranges = V; VCC = V ± 10%; -M and -V ranges V; 2.7 V < VCC < 5.5 V; -L range = V; 2.7 V < VCC < 5.5 V; -L range Table 24 gives the maximum applicable load capacitance for Port 0, Port 1, and 3, and ALE and PSEN signals Timings will be guaranteed if these capacitances are respected Higher capacitance values can be used, but timings will then be degraded Table 24 Load Capacitance versus speed range, in pF -M 100 80 100 Port Port 1, 2, ALE / PSEN -V 50 50 30 -L 100 80 100 Table 26., Table 29 and Table 32 give the description of each AC symbols Table 27., Table 30 and Table 33 give for each range the AC parameter Table 28., Table 31 and Table 34 give the frequency derating formula of the AC parameter To calculate each AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value in the formula Values of the frequency must be limited to the corresponding speed grade: Table 25 Max frequency for derating formula regarding the speed grade Freq (MHz) T (ns) -M X1 mode 40 25 -M X2 mode 20 50 -V X1 mode 40 25 -V X2 mode 30 33.3 -L X1 mode 30 33.3 -L X2 mode 20 50 Example: TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns): x= 22 (Table 28.) T= 50ns TLLIV= 2T - x = x 50 - 22 = 78ns 44 Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 10.5.2 External Program Memory Characteristics Table 26 Symbol Description Symbol T Parameter Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction FloatAfter PSEN TPXAV PSEN to Address Valid TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float Table 27 AC Parameters for Fix Clock Speed -M 40 MHz Max -V X2 mode 30 MHz 60 MHz equiv Min Min 25 33 25 50 33 ns TLHLL 40 25 42 35 52 ns TAVLL 10 12 13 ns TLLAX 10 12 13 ns 78 Max Min Units T 45 Max -L standard mode 30 MHz Min 70 Max -L X2 mode 20 MHz 40 MHz equiv Symbol TLLIV Min -V standard mode 40 MHz 65 Max 98 ns TLLPL 15 17 10 18 ns TPLPH 55 35 60 50 75 ns TPLIV TPXIX 35 25 50 30 55 ns ns TPXIZ 18 12 20 10 18 ns TAVIV 85 53 95 80 122 ns TPLAZ 10 10 10 10 10 ns Rev.D - 16 November, 2000 45 TS80C32X2 TS87C52X2 TS80C52X2 Table 28 AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock X2 Clock -M -V -L Units TLHLL Min 2T-x T-x 10 15 ns TAVLL Min T-x 0.5 T - x 15 13 20 ns TLLAX Min T-x 0.5 T - x 15 13 20 ns TLLIV Max 4T-x 2T-x 30 22 35 ns TLLPL Min T-x 0.5 T - x 10 15 ns TPLPH Min 3T-x 1.5 T - x 20 15 25 ns TPLIV Max 3T-x 1.5 T - x 40 25 45 ns TPXIX Min x x 0 ns TPXIZ Max T-x 0.5 T - x 15 ns TAVIV Max 5T-x 2.5 T - x 40 30 45 ns TPLAZ Max x x 10 10 10 ns 10.5.3 External Program Memory Read Cycle 12 TCLCL TLHLL TLLIV ALE TLLPL TPLPH PSEN TLLAX TAVLL PORT INSTR IN TPLIV TPLAZ A0-A7 TPXAV TPXIZ TPXIX INSTR IN A0-A7 INSTR IN TAVIV PORT ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 Figure 18 External Program Memory Read Cycle 46 Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 10.5.4 External Data Memory Characteristics Table 29 Symbol Description Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high Rev.D - 16 November, 2000 47 TS80C32X2 TS87C52X2 TS80C52X2 Table 30 AC Parameters for a Fix Clock Speed -M 40 MHz 85 135 125 175 ns TWLWH 130 85 135 125 175 ns 60 Max Min 102 Max Min Units 130 Min -L standard mode 30 MHz TRLRH 100 Max -L X2 mode 20 MHz 40 MHz equiv Min TRHDX Min -V standard mode 40 MHz Symbol TRLDV Max -V X2 mode 30 MHz 60 MHz equiv 95 Max 137 ns ns TRHDZ 30 18 35 25 42 ns TLLDV 160 98 165 155 222 ns TAVDV 165 100 175 160 235 ns 130 ns TLLWL 50 TAVWL 75 47 80 70 103 ns TQVWX 10 15 13 ns TQVWH 160 107 165 155 213 ns TWHQX 15 17 10 18 ns TRLAZ TWHLH 48 100 30 10 40 70 55 27 95 45 15 35 105 70 45 13 ns 53 ns Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 Table 31 AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock X2 Clock -M -V -L Units TRLRH Min 6T-x 3T-x 20 15 25 ns TWLWH Min 6T-x 3T-x 20 15 25 ns TRLDV Max 5T-x 2.5 T - x 25 23 30 ns TRHDX Min x x 0 ns TRHDZ Max 2T-x T-x 20 15 25 ns TLLDV Max 8T-x 4T -x 40 35 45 ns TAVDV Max 9T-x 4.5 T - x 60 50 65 ns TLLWL Min 3T-x 1.5 T - x 25 20 30 ns TLLWL Max 3T+x 1.5 T + x 25 20 30 ns TAVWL Min 4T-x 2T-x 25 20 30 ns TQVWX Min T-x 0.5 T - x 15 10 20 ns TQVWH Min 7T-x 3.5 T - x 15 10 20 ns TWHQX Min T-x 0.5 T - x 10 15 ns TRLAZ Max x x 0 ns TWHLH Min T-x 0.5 T - x 15 10 20 ns TWHLH Max T+x 0.5 T + x 15 10 20 ns 10.5.5 External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TLLAX PORT A0-A7 TQVWX TQVWH TWHQX DATA OUT TAVWL PORT ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 Figure 19 External Data Memory Write Cycle Rev.D - 16 November, 2000 49 TS80C32X2 TS87C52X2 TS80C52X2 10.5.6 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH TRLDV RD TLLAX PORT TRHDZ TAVDV TRHDX A0-A7 DATA IN TRLAZ TAVWL ADDRESS OR SFR-P2 PORT ADDRESS A8-A15 OR SFR P2 Figure 20 External Data Memory Read Cycle 10.5.7 Serial Port Timing - Shift Register Mode Table 32 Symbol Description Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid Table 33 AC Parameters for a Fix Clock Speed -M 40 MHz Max 200 300 300 400 ns TQVHX 200 117 200 200 283 ns TXHQX 30 13 30 30 47 ns TXHDX 0 0 ns 117 Min Max 117 Min Units 300 34 Min -L standard mode 30 MHz TXLXL 50 Max -L X2 mode 20 MHz 40 MHz equiv Min 117 Min -V standard mode 40 MHz Symbol TXHDV Max -V X2 mode 30 MHz 60 MHz equiv Max 200 ns Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 Table 34 AC Parameters for a Variable Clock: derating formula -M -V Units Symbol Type Standard Clock X2 Clock -L TXLXL Min 12 T 6T TQVHX Min 10 T - x 5T-x 50 50 50 ns TXHQX Min 2T-x T-x 20 20 20 ns TXHDX Min x x 0 ns TXHDV Max 10 T - x T- x 133 133 133 ns ns 10.5.8 Shift Register Timing Waveforms INSTRUCTION ALE TXLXL CLOCK TXHQX TQVXH OUTPUT DATA WRITE to SBUF TXHDV INPUT DATA TXHDX VALID VALID VALID SET TI VALID VALID VALID VALID VALID SET RI CLEAR RI Figure 21 Shift Register Timing Waveforms Rev.D - 16 November, 2000 51 TS80C32X2 TS87C52X2 TS80C52X2 10.5.9 EPROM Programming and Verification Characteristics TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10% while programming VCC = operating range while verifying Table 35 EPROM Programming Parameters Parameter Symbol VPP Max Units 12.5 13 V 75 Programming Supply Voltage IPP Min mA MHz Programming Supply Current 1/TCLCL Oscillator Frquency TAVGL Address Setup to PROG Low 48 TCLCL TGHAX Adress Hold after PROG 48 TCLCL TDVGL Data Setup to PROG Low 48 TCLCL TGHDX Data Hold after PROG 48 TCLCL TEHSH (Enable) High to VPP 48 TCLCL TSHGL VPP Setup to PROG Low 10 µs TGHSL VPP Hold after PROG 10 µs TGLGH PROG Width 90 TAVQV Address to Valid Data 48 TCLCL TELQV ENABLE Low to Data Valid 48 TCLCL TEHQZ Data Float after ENABLE µs 110 48 TCLCL 10.5.10 EPROM Programming and Verification Waveforms PROGRAMMING VERIFICATION ADDRESS ADDRESS P1.0-P1.7 P2.0-P2.5 P3.4-P3.5* TAVQV P0 DATA OUT DATA IN TGHDX TGHAX TDVGL TAVGL ALE/PROG TSHGL TGLGH EA/VPP CONTROL SIGNALS (ENABLE) TGHSL VPP VCC TEHSH VCC TELQV TEHQZ * 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5 Figure 22 EPROM Programming and Verification Waveforms 52 Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 10.5.11 External Clock Drive Characteristics (XTAL1) Table 36 AC Parameters Symbol Parameter Min Max Units TCLCL Oscillator Period 25 ns TCHCX High Time ns TCLCX Low Time ns TCLCH Rise Time ns TCHCL Fall Time ns 60 % TCHCX/TCLCX Cyclic ratio in X2 mode 40 10.5.12 External Clock Drive Waveforms VCC-0.5 V 0.7VCC 0.2VCC-0.1 V TCHCL 0.45 V TCHCX TCLCH TCLCX TCLCL Figure 23 External Clock Drive Waveforms 10.5.13 AC Testing Input/Output Waveforms VCC-0.5 V INPUT/OUTPUT 0.2VCC+0.9 0.2VCC-0.1 0.45 V Figure 24 AC Testing Input/Output Waveforms AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0” Timing measurement are made at VIH for a logic “1” and VIL max for a logic “0” 10.5.14 Float Waveforms FLOAT VOH-0.1 V VLOAD VOL+0.1 V VLOAD+0.1 V VLOAD-0.1 V Figure 25 Float Waveforms Rev.D - 16 November, 2000 53 TS80C32X2 TS87C52X2 TS80C52X2 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs IOL/IOH ≥ ± 20mA 10.5.15 Clock Waveforms Valid in normal clock mode In X2 mode XTAL2 signal must be changed to XTAL2 divided by two STATE4 INTERNAL CLOCK P1 P2 STATE5 STATE6 STATE1 STATE2 P1 P1 P1 P1 P2 P2 P2 P2 STATE3 P1 P2 STATE4 P1 P2 STATE5 P1 P2 XTAL2 ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED PCL OUT DATA SAMPLED FLOAT P2 (EXT) PCL OUT DATA SAMPLED PCL OUT FLOAT FLOAT INDICATES ADDRESS TRANSITIONS READ CYCLE RD PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt OUT FLOAT P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION WRITE CYCLE WR P0 PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) DPL OR Rt OUT DATA OUT P2 PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) INDICATES DPH OR P2 SFR TO PCH TRANSITION PORT OPERATION OLD DATA P0 PINS SAMPLED NEW DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1, P2, P3) (INCLUDES INT0, INT1, TO, T1) P1, P2, P3 PINS SAMPLED SERIAL PORT SHIFT CLOCK TXD (MODE 0) RXD SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED Figure 26 Clock Waveforms This diagram indicates when signals are clocked internally The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns This propagation delay is dependent on variables such as temperature and pin loading Propagation also varies from output to output and component Typically though (TA=25°C fully loaded) RD and WR propagation delays are approximately 50ns The other signals are typically 85 ns Propagation delays are incorporated in the AC specifications 54 Rev.D - 16 November, 2000 TS80C32X2 TS87C52X2 TS80C52X2 11 Ordering Information TS -M 87C52X2 -M: -V: -L: -E: C R B Packages: A: PDIL 40 B: PLCC 44 C: PQFP F1 (13.9 mm footprint) E: VQFP 44 (1.4mm) VCC: 5V +/- 10% 40 MHz, standard mode 20 MHz, X2 mode VCC: 5V +/- 10% 40 MHz, standard mode 30 MHz, X2 mode VCC: 2.7 to 5.5 V 30 MHz, standard mode 20 MHz, X2 mode Samples EPROM-UV Erasable (*) J: Window CDIL 40* K: Window CQPJ 44* Part Number 80C32X2: Romless 80C52X2: 8K ROM 87C52X2: 8K OTP Conditioning R: Tape & Reel D: Dry Pack B: Tape & Reel and Dry Pack Temperature Range C: Commercial to 70oC I: Industrial -40 to 85oC (*) Check with Atmel Wireless & Microcontrollers Sales Office for availability Ceramic packages (J, K) are available for prototyping, not for volume production Table 37 Maximum Clock Frequency Code -M -V -L Standard Mode, oscillator frequency Standard Mode, internal frequency X2 Mode, oscillator frequency X2 Mode, internal equivalent frequency 40 40 20 40 40 40 30 60 30 30 20 40 Rev.D - 16 November, 2000 Unit MHz MHz 55 TS80C32X2 TS87C52X2 TS80C52X2 Table 38 Possible Ordering Entries TS80C32X2 -MCA -MCB -MCC -MCE -VCA -VCB -VCC -VCE -LCA -LCB -LCC -LCE -MIA -MIB -MIC -MIE -VIA -VIB -VIC -VIE -LIA -LIB -LIC -LIE -EA -EB -EC -EE -EJ -EK TS80C52zzz ROM TS87C52 OTP X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X q -Ex for samples q Tape and Reel available for B, C and E packages q Dry pack mandatory for E packages 56 Rev.D - 16 November, 2000 ... execution and reduce code size in a number of ways The dual DPTR structure is a way by which the chip will specify the address of an external data memory location There are two 16-bit DPTR registers... leave port floating Rev.D - 16 November, 2000 29 TS80C32X2 TS87C52X2 TS80C52X2 6.8 ONCETM Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C52X2 without... bytes 7.2 ROM Lock System The program Lock system, when programmed, protects the on -chip program against software piracy 7.2.1 Encryption Array Within the ROM array are 64 bytes of