... 6.002 Fall 2000 Lecture 1 4 6.002 CIRCUITS AND ELECTRONICS The Digital Abstraction 6.002 Fall 2000 Lecture 2 4 Review z Discretize matter ... learned in the previous three lectures are sufficient to analyze simple digital circuits Reading: Chapter 5 of Agarwal & Lang Today 6.002 Fall 2000 Lecture 4 4 Analog signal processing But first, ... superposition, Thévenin, Norton (remember s...
... 6.002 Fall 2000 Lecture 1 2 6.002 CIRCUITS AND ELECTRONICS Basic Circuit Analysis Method (KVL and KCL method) 6.002 Fall 2000 Lecture 2 ... =+−+− GeGeeGVe KCL at 1 e 0)()()( 152402312 =−+−+− IGeGVeGee KCL at 2 l move constant terms to RHS & collect unknowns )()()( 10323211 GVGeGGGe =−+++ 140543231 )()()( IGVGGGeGe +=+++− i i R G
... 6.002 CIRCUITS AND ELECTRONICS Introduction and Lumped Circuit Abstraction 6.002 Fall 2000 Lecture 1 1 ADMINISTRIVIA Lecturer: Prof. Anant Agarwal Textbook: Agarwal and Lang (A&L) ... let’s assume this 6.002 Fall 2000 Lecture 1 16 f r o m M a x we l V Must also be defined. s e e A & L So let’s assume this too V AB So V AB = ∫ AB E ⋅ dl defined when 0 = ∂ ∂ t B φ outside elemen...
... D S TGS Vv < G TGS Vv ≥ ON R D S G e.g. Ω= KR ON 5 6.002 Fall 2000 Lecture 19 5 SR Model of MOSFET MOSFET S model TGS Vv ≥ TGS Vv < DS i DS v MOSFET SR model TGS Vv ≥ TGS Vv < DS i DS ... . TGS Vv < TGS Vv ≥ VV T 1≈ typically on G D S DS i G off D S 6.002 Fall 2000 Lecture 14 5 Check the MOS device on a scope. Demo GS v + – DS v DS i + – TGS Vv ≥ DS i DS v TGS Vv < DS i ... 6.0...
... 6.002 Fall 2000 Lecture 1 3 6.002 CIRCUITS AND ELECTRONICS Superposition, Thévenin and Norton 6.002 Fall 2000 Lecture 2 3 0= ∑ loop i V ... external excitation and behaves like a voltage “ ” TH v also independent of external excitement & behaves like a resistor 6.002 Fall 2000 Lecture 16 3 Or iRvv THTH += As far as the external
... 6.002
CIRCUITS
AND
ELECTRONICS
Sinusoidal Steady State
6.002 Fall 2000 Lecture
16
1
2
Fourth try to find ...
+
–
R
i
C
+
v
I
v
C
–
v
I
(
t
)
= V
i
cos
ω
t
for
t ≥
0 (
V
i
real)
= 0
for
t <
0
v
C
(0)
=
0
for
t =
0
I
v
0
t
6.002 Fall 2000 Lecture
16
4
1
1
1
1
e
c
t
u
r
Example:
... 6.002 Fall 2000 Lecture
1
15
6.002
CIRCUITS
AND
ELECTRONICS
Second-Order Systems
6.002 Fall 2000 Lecture
10
15
0
2
2
=+
H
H
v
d
t
vd
LC
Solution ... back and forth between the
Capacitor and the inductor
6.002 Fall 2000 Lecture
19
15
RLC Circuits
See A&L Section 12.2
add
R
no
R
+
–
C
R
L
+
–
)(
tv
)(tv
I
)(
ti
)(
tv
t
Damped sinusoids ... Method
1
2
3
Write DE for circuit by a...
... 6.002 Fall 2000 Lecture
1
14
6.002
CIRCUITS
AND
ELECTRONICS
State and Memory
6.002 Fall 2000 Lecture
10
14
A
Stored value leaks away
store
pulse width >>
R
ON
C
Building a memory element ... resistance
R
IN
B
Second attempt buffer
R
IN
store
buffer
d
IN
d
OUT
C
*
5
ln
OH
IN
V
CRT −=
LIN
RR >>
Better, but still not perfect.
Demo
Building a memory element …
6.002 Fall 20...
... 6.002 Fall 2000 Lecture
1
12
6.002
CIRCUITS
AND
ELECTRONICS
Capacitors
and First-Order Systems
6.002 Fall 2000 Lecture
10
12
2
Homogeneous ... 55
RC
t
e
−
5
RC
=
τ
Remember
demo
B
Examples
6.002 Fall 2000 Lecture
2
12
5V
0V
C
A
B
5V
A
B
C
5
0
5
0
5
0
Reading:
Chapters 9 & 10
Demo
5V
Expected
Observed
Expect this, right?
But observe this!
Delay!
Motivation
6.002