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Systems Programming 8086/88 Memory Interface II CMPE 3101 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory Address DecodingThe processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. In order to splice a memory device into the address space of the processor, decoding is necessary.For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space. However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space. Systems Programming 8086/88 Memory Interface II CMPE 3102 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory Address DecodingA0A1A10O0O1O7 CSRD of 8088/862716IO/MA19A18A17A16A15A14A13A12A11Address Bus Data BusLogic 0 when A11 through A19 are all 1.Or MRDC bus signal.(2K X 8)(Book showsOE connectionfor RD butchip definitiondoes NOT haveEPROMthis pin). Systems Programming 8086/88 Memory Interface II CMPE 3103 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory Address DecodingTo determine the address range that a device is mapped into:This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H).NAND gate decoders are not often used.Rather the 3-to-8 Line Decoder (74LS138) is more common.1111 1111 1XXX XXXX XXXXA19 - A11A10 - A01111 1111 1000 0000 0000 (FF800H)To1111 1111 1111 1111 1111 (FFFFFH) Systems Programming 8086/88 Memory Interface II CMPE 3104 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory Address DecodingThe 3-to-8 Line Decoder (74LS138)Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high, respectively.Each output of the decoder can be attached to an 2764 EPROM (8K X 8).G2AG2BG1ABC01234567EnableSelect InputsOutputsInputsOutputEnable SelectG2A G2B G1C B A 0 1 2 3 4 5 6 71 X X X X X 1 1 1 1 1 1 1 1X 1 X X X X 1 1 1 1 1 1 1 1X X 0 X X X 1 1 1 1 1 1 1 10 0 1 0 0 0 0 1 1 1 1 1 1 10 0 1 0 0 1 1 0 1 1 1 1 1 10 0 1 0 1 0 1 1 0 1 1 1 1 10 0 1 0 1 1 1 1 1 0 1 1 1 10 0 1 1 0 0 1 1 1 1 0 1 1 10 0 1 1 0 1 1 1 1 1 1 0 1 10 0 1 1 1 0 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 1 1 1 0 Systems Programming 8086/88 Memory Interface II CMPE 3105 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory Address DecodingThe EPROMs cover a 64KB section of memory.G2AG2BG1ABC01234567A0A12O0O7 . .CS2764A16A17A18A19A13A14A15CSCSCSCSCSCSCSRD of 8088/86Data BusAddress BusF2000-F3FFFF0000-F1FFFF4000-F5FFFF6000-F7FFFF8000-F9FFFFA000-FBFFFFC000-FDFFFFE000-FFFFFAddress spaceF0000H-FFFFFHA13 through A15 selecta 2764A16 through A19 enablethe decoder(8K X 8)(Not sure about 2764 pinout,text is in error with 2716)74LS138EPROM Systems Programming 8086/88 Memory Interface II CMPE 3106 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory Address DecodingYet a third possibility is a PLD (Programmable Logic Device).PLDs come in three varieties:• PLA (Programmable Logic Array)• PAL (Programmable Array Logic)• GAL (Gated Array Logic)PLDs have been around since the mid-1970s but have only recently appeared in memory systems (PALs have replaced PROM address decoders).PALs and PLAs are fuse-programmed (like the PROM).Some are erasable (like the EPROM).A PAL example (16L8) is shown in the text and is commonly used to decode the memory address, particularly for 32-bit addresses generated by the 80386DX and above. Systems Programming 8086/88 Memory Interface II CMPE 3107 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory Address DecodingAMD 16L8 PAL decoder.It has 10 fixed inputs (Pins 1-9, 11), two fixed outputs (Pins 12 and 19) and 6 pins that can be either (Pins 13-18).AND/NOR device with logic expressions (outputs) with up to 16 ANDed inputs and 7 ORed product terms.O31234567151120191616L81718I4I5I6I7VCCI3I2O6O8I1O4O5O79810121314I8I9GNDO2O1I10;pins 1 2 3 4 5 6 7 8 9 10A19 A18 A17 A16 A15 A14 A13 NC NC GND;pins 11 12 13 14 15 16 17 18 19 20NC O8 O7 O6 O5 O4 O3 O2 O1 VCCEquations:/O1 = A19 * A18 * A17 * A16 * /A15 * /A14 * /A13/O2 = A19 * A18 * A17 * A16 * /A15 * /A14 * A13/O3 = A19 * A18 * A17 * A16 * /A15 * A14 * /A13/O4 = A19 * A18 * A17 * A16 * /A15 * A14 * A13/O5 = A19 * A18 * A17 * A16 * A15 * /A14 * /A13/O6 = A19 * A18 * A17 * A16 * A15 * /A14 * A13/O7 = A19 * A18 * A17 * A16 * A15 * A14 * /A13/O8 = A19 * A18 * A17 * A16 * A15 * A14 * A13Programmed to decode address lines A19 - A13 onto 8 outputs. Systems Programming 8086/88 Memory Interface II CMPE 3108 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68088 and 80188 (8-bit) Memory InterfaceThe memory systems “sees” the 8088 as a device with:• 20 address connections (A19 to A0).• 8 data bus connections (AD7 to AD0).• 3 control signals, IO/M, RD, and WR.We’ll look at interfacing the 8088 with:• 32K of EPROM (at addresses F8000H through FFFFFH).• 512K of SRAM (at addresses 00000H through 7FFFFH).The EPROM interface uses a 74LS138 (3-to-8 line decoder) plus 8 2732 (4K X 8) EPROMs.The EPROM will also require the generation of a wait state.The EPROM has an access time of 450ns.The 74LS138 requires 12ns to decode.The 8088 runs at 5MHz and only allows 460ns for memory to access data.A wait state adds 200ns of additional time. Systems Programming 8086/88 Memory Interface II CMPE 3109 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68088 and 80188 (8-bit) EPROM Memory InterfaceThe 8088 cold starts execution at FFFF0H. JMP to F8000H occurs here.G2AG2BG1ABC01234567A0A11O0O7 . .CS2732A15A17A18A19A12A13A14CSCSCSCSCSCSCSRDData BusAddress BusAddress spaceF8000H-FFFFFH(4K X 8)(This is the 2732 pinoutas shown in the text.)74LS138OEA16WAITIO/M5V1KTo wait state generator Systems Programming 8086/88 Memory Interface II CMPE 31010 (April 10, 2000 12:36 pm)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68088 and 80188 (8-bit) RAM Memory InterfaceA0A14O0O7 CSA18A19CSCSCSCSCSCSCSOEIO/MWECSCSCSCSCSCSCSA0A14O0O7 CSOEWEData Bus(32K X 8)WRA15A16A171G 2G74LS244BufferRDGDir74LS245BD BufferG2AG2BG1ABC01234567G2AG2BG1ABC01234567Address Bus74LS138A14A9A10A11A12A131G 2G74LS244BufferA8G2AG2BG1ABC01234567A6A7A0A1A2A3A4A51G 2G74LS244Buffer62256(32K X 8)622563274LS13874LS1384 [...]... also be interfaced to the 80 88 (see text) However, the write time (400ms !) is too slow to be used as RAM (as shown in the text) 80 88 and 80 188 ( 8- bit) RAM Memory Interface The 16 62256s on the previous slide are actually SRAMs Access times are on order of 10ns Systems Programming MO UN TI RE COUNT Y IVERSITY O F M 1966 14 13 12 11 10 9 8 VCC F E D C B A L H H L 0, 2, 4, 6, 8 1, 3, 5, 7, 9 UMBC 12 (April... EVEN ODD 80 86 /88 Memory Interface II 9-bit parity generator/checker G H NC I EVEN ODD GND 74AS 280 Parity for Memory Error Detection 74AS 280 Parity Generator/Checker Systems Programming MO UN TI RE COUNT Y M YLAND BA L TI MO 1966 U M B C AR 0 1 2 3 G1 4 5 G2A 6 G2B 7 A B C 74LS1 38 UMBC RESET NMI A19 A 18 IO/M A15 A16 A17 WR RD Address Bus Parity for Memory Error Detection 13 O0 A14 O7 A0 80 86 /88 Memory... +X 2 27 26 25 24 22 21 18 +X +1 X +X +X +X +X +X +X Final Solution is: 16 16 27 26 25 24 22 21 18 M ( X )X X +X +X +X +X +X +X - = -G(X) 16 15 2 X +X +X +1 IVERSITY O F + 80 86 /88 Memory Interface II Error Detection • Cyclic Redundancy Check (CRC)(cont.) Systems Programming MO UN TI RE COUNT Y IVERSITY O F 80 86 /88 Memory Interface II M YLAND... (32K X 8) A0 DO DI A15 WE OE CS 62256 (32K X 8) Systems Programming IVERSITY O F WE CE UN 6 287 (64K X 1) D Data Bus (April 10, 2000 12:36 pm) CLK Clear Q Q A EVEN B C ODD D E F G H I Checker Generator A EVEN B ODD C D E F G H I CMPE 310 74LS 280 74LS 280 74LS74 RE COUNT Y 80 86 /88 Memory Interface II CMPE 310 IVERSITY O F M YLAND BA L 1966 U M B C AR 0111 1100 + 1 1000 0011 + 1 1000 0100 = 84 H Invert... following equation Systems Programming MO UN TI RE COUNT Y X +X 15 X 27 M +X 8 6 4 3 17 18 X X 17 17 +X + 18 + 11 13 16 X 13 X + 13 + + + + 9 4 2 X +X 9 8 6 4 2 X +X +X +X +X 3 X +X 9 8 6 X +X +X X 8 6 X +X 9 6 2 +X +X +X +X+1 13 11 X +X 13 11 X +X 11 9 X +X X +X + +X +X +X +X +X +X+1 9 X X 22 21 18 X +X +X 22 21 X +X 25 24 22 21 18 X +X +X +X +X 25 24 + X +X + X CMPE 310 YLAND BA L 1966 U M B C AR UMBC... Systems Programming MO UN TI RE COUNT Y IVERSITY O F 80 86 /88 Memory Interface II CMPE 310 M YLAND BA L 1966 U M B C AR n–1 + b0 X n 2 10 9 3 4 5 6 7 8 5 6 + 1X + 0X 8 11 9 12 UMBC 15 13 + 1X 14 11 + 0X + 0X 15 (April 10, 2000 12:36 pm) 10 + 0X M ( X ) = 1X + 1X + 1X + 1X + 1X + 1X 2 1X + 1X M ( X ) = 0 + 0X + 1X + 0X + 0X + 1X + 1X + 0X + 1X + 1 For the 16-bit data stream: 26F0H = 0010 0110 1111 0000 where...IVERSITY O F 80 86 /88 Memory Interface II M 1966 UMBC 11 (April 10, 2000 12:36 pm) For 72-pin SIMMs, the number of data bits is 32 + 4 = 36 (4 parity bits) Parity checking adds 1 bit for every 8 data bits • For EVEN parity, the 9th bit is set to yield an even number of 1’s in all 9 bits • For ODD parity,... parity is now 1 P3 even parity is 0 P4 even parity is now 1 If X10 flips from 0 -> 1, then the check gives the location of the bit error as: Parity encoded data: 110110010011 Error Correction Hamming Codes (cont) Systems Programming MO UN TI RE COUNT Y IVERSITY O F 80 86 /88 Memory Interface II M YLAND BA L 1966 U M B C AR 20 19 18 17 16 15 14 13 12 11 VCC SEF S1 S0 CB0 CB1 CB2 CB3 NC CB4 UMBC 21 See the... Redundancy Check (CRC) Commonly used to check data transfers in hardware such as harddrives Treats data as a stream of serial data n-bits long The bits are treated as coefficients of a characteristic polynomial, M(X) of the form: Systems Programming MO UN TI RE COUNT Y IVERSITY O F 80 86 /88 Memory Interface II M YLAND BA L 1966 U M B C AR Q(X) is the quotient R(X) is the remainder CMPE 310 16 +X 15 2 +X +1 UMBC... is 1 Not used since we are correcting byte data Error Correction Hamming Codes (cont) P1 is generated by computing the parity of X3, X5, X7, X9, X11, X13, X15 Systems Programming MO UN TI RE COUNT Y 80 86 /88 Memory Interface II IVERSITY O F CMPE 310 M YLAND BA L 1966 U M B C AR 7 0 0 0 0 6 0 0 0 0 UMBC Flipped P 12 11 10 9 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 5 1 1 1 1 3 0 0 0 0 Since these are NOT . )-- -- - -- - -- - -- - -- - -- - -- - -X27X26X25X24X22X21X 18+ + + + + +X16X15X21+ + +-- -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - =X16X15X21+. +-- -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - =X16X15X21+ + + X27X26X25X24X22X21X 18+ + + + + +X27X26+X13X11++X25X24X22X21X 18+ + + +X25X24+X11X9+X22X21X 18+ +X9++X22X21+X8X6++X18X9X8X6+