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(BQ) Part 2 book CMOS VLSI design A circuits and systems perspective has contents: Combinational circuit design, sequential circuit design, datapath subsystems, array subsystems, special purpose subsystems, special purpose subsystems; testing, debugging, and verification,... and other contents.
Combinational Circuit Design 9.1 Introduction Digital logic is divided into combinational and sequential circuits Combinational circuits are those whose outputs depend only on the present inputs, while sequential circuits have memory Generally, the building blocks for combinational circuits are logic gates, while the building blocks for sequential circuits are registers and latches This chapter focuses on combinational logic; Chapter 10 examines sequential logic In Chapter 1, we introduced CMOS logic with the assumption that MOS transistors act as simple switches Static CMOS gates used complementary nMOS and pMOS networks to drive and outputs, respectively In Chapter 4, we used the RC delay model and logical effort to understand the sources of delay in static CMOS logic In this chapter, we examine techniques to optimize combinational circuits for lower delay and/or energy The vast majority of circuits use static CMOS because it is robust, fast, energy-efficient, and easy to design However, certain circuits have particularly stringent speed, power, or density restrictions that force another solution Such alternative CMOS logic configurations are called circuit families Section 9.2 examines the most commonly used alternative circuit families: ratioed circuits, dynamic circuits, and passtransistor circuits The decade roughly spanning 1994–2004 was the heyday of dynamic circuits, when high-performance microprocessors employed ever-more elaborate structures to squeeze out the highest possible operating frequency Since then, power, robustness, and design productivity considerations have eliminated dynamic circuits wherever possible, although they remain important for memory arrays where the alternatives are painful Similarly, other circuit families have been removed or relegated to narrow niches Recall from Section 4.3.7 that the delay of a logic gate depends on its output current I, load capacitance C, and output voltage swing )V C (9.1) )V I Faster circuit families attempt to reduce one of these three terms nMOS transistors provide more current than pMOS for the same size and capacitance, so nMOS networks are preferred Observe that the logical effort is proportional to the C/I term because it is determined by the input capacitance of a gate that can deliver a specified output current One drawback of static CMOS is that it requires both nMOS and pMOS transistors on each input During a falling output transition, the pMOS transistors add significant capacitance without helping the pulldown current; hence, static CMOS has a relatively large logical effort Many faster circuit families seek to drive only nMOS transistors with the inputs, thus reducing capacitance and logical effort An alternative mechanism must be provided to tx 327 328 Chapter Combinational Circuit Design pull the output high Determining when to pull outputs high involves monitoring the inputs, outputs, or some clock signal Monitoring inputs and outputs inevitably loads the nodes, so clocked circuits are often fastest if the clock can be provided at the ideal time Another drawback of static CMOS is that all the node voltages must transition between and VDD Some circuit families use reduced voltage swings to improve propagation delays (and power consumption) This advantage must be weighed against the delay and power of amplifying outputs back to full levels later or the costs of tolerating the reduced swings Static CMOS logic is particularly popular because of its robustness Given the correct inputs, it will eventually produce the correct output so long as there were no errors in logic design or manufacturing Other circuit families are prone to numerous pathologies examined in Section 9.3, including charge sharing, leakage, threshold drops, and ratioing constraints When using alternative circuit families, it is vital to understand the failure mechanisms and check that the circuits will work correctly in all design corners A host of other circuit families have been proposed, but most have never been used in commercial products and are doomed to reside on dusty library shelves Every transistor contributes capacitance, so most fast structures are simple Nevertheless, we will describe some of these circuits in Section 9.4 as a record of ideas that have been explored A few hold promise for the future, particularly in specialized applications Many texts simply catalog these circuit families without making judgments This book attempts to evaluate the circuit families so that designers can concentrate their efforts on the most promising ones, rather than searching for the “gotchas” that were not mentioned in the original papers Of course, any such evaluation runs the risk of overlooking advantages or becoming incorrect as technology changes, so you should use your own judgment Silicon-on-insulator (SOI) chips eliminate the conductive substrate They can achieve lower parasitic capacitance and better subthreshold slopes, leading to lower power and/or higher speed, but they have their own special pathologies Section 9.5 examines considerations for SOI circuits CMOS is increasingly applied to ultra-low power systems such as implantable medical devices that require years of operation off of a tiny battery and remote sensors that scavenge their energy from the environment Static CMOS gates operating in the subthreshold regime can cut the energy per operation by an order of magnitude at the expense of several orders of magnitude performance reduction Section 9.6 explores design issues for subthreshold circuits 9.2 Circuit Families Static CMOS circuits with complementary nMOS pulldown and pMOS pullup networks are used for the vast majority of logic gates in integrated circuits They have good noise margins, and are fast, low power, insensitive to device variations, easy to design, widely supported by CAD tools, and readily available in standard cell libraries When noise does exceed the margins, the gate delay increases because of the glitch, but the gate eventually will settle to the correct answer Most design teams now use static CMOS exclusively for combinational logic This section begins with a number of techniques for optimizing static CMOS circuits Nevertheless, performance or area constraints occasionally dictate the need for other circuit families The most important alternative is dynamic circuits However, we begin by considering ratioed circuits, which are simpler and offer a helpful conceptual transition between static and dynamic We also consider pass transistors, which had their zenith in the 1990s for general-purpose logic and still appear in specialized applications 9.2 Circuit Families 329 9.2.1 Static CMOS Designers accustomed to AND and OR functions must learn to think in terms of NAND and NOR to take advantage of static CMOS In manual circuit design, this is often done through bubble pushing Compound gates are particularly useful to perform complex functions with relatively low logical efforts When a particular input is known to be latest, the gate can be optimized to favor that input Similarly, when either the rising or falling edge is known to be more critical, the gate can be optimized to favor that edge We have focused on building gates with equal rising and falling delays; however, using smaller pMOS transistors can reduce power, area, and delay In processes with multiple threshold voltages, multiple flavors of gates can be constructed with different speed/leakage power trade-offs 9.2.1.1 Bubble Pushing CMOS stages are inherently inverting, so AND and OR functions must be built from NAND and NOR gates DeMorgan’s law helps with this conversion: AB = A + B (9.2) A+B = AB These relations are illustrated graphically in Figure 9.1 A NAND gate is equivalent to an OR of inverted inputs A NOR gate is equivalent to an AND of inverted inputs The same relationship applies to gates with more inputs Switching between these representations is easy to on a whiteboard and is often called bubble pushing Example 9.1 FIGURE 9.1 Bubble pushing Design a circuit to compute F = AB + CD using NANDs and NORs with DeMorgan’s law SOLUTION: By inspection, the circuit consists of two ANDs and an OR, shown in Figure 9.2(a) In Figure 9.2(b), the ANDs and ORs are converted to basic CMOS stages In Figure 9.2(c and d), bubble pushing is used to simplify the logic to three NANDs A B A B F F C D C D (a) (b) A B A B F F C D C D (c) (d) FIGURE 9.2 Bubble pushing to convert ANDs and ORs to NANDs and NORs 9.2.1.2 Compound Gates As described in Section 1.4.5, static CMOS also efficiently handles compound gates computing various inverting combinations of AND/OR functions in a single stage The function F = AB + CD can be computed with an AND-ORINVERT-22 (AOI22) gate and an inverter, as shown in Figure 9.3 A B C D F FIGURE 9.3 Logic using AOI22 gate 330 Chapter Combinational Circuit Design In general, logical effort of compound gates can be different for different inputs Figure 9.4 shows how logical efforts can be estimated for the AOI21, AOI22, and a more complex compound AOI gate The transistor widths are chosen to give the same drive as a unit inverter The logical effort of each input is the ratio of the input capacitance of that input to the input capacitance of the inverter For the AOI21 gate, this means the logical effort is slightly lower for the OR terminal (C) than for the two AND terminals (A, B) The parasitic delay is crudely estimated from the total diffusion capacitance on the output node by summing the sizes of the transistors attached to the output Unit Inverter AOI21 Y=A A Y Y A Y B C 4 A B C Y Complex AOI Y=A·B+C·D A B C A AOI22 Y=A·B+C A B C D Y = A · (B +C) + D · E Y D E A B C Y A B B C D C A A C D E B D E A D 2 C Y B gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3 p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3 gC = 5/3 gC = 6/3 gC = 8/3 p = 7/3 gD = 6/3 gD = 8/3 p = 12/3 gE = 8/3 Y p = 16/3 FIGURE 9.4 Logical efforts and parasitic delays of AOI gates Example 9.2 Calculate the minimum delay, in Y, to compute F = AB + CD using the circuits from Figure 9.2(d) and Figure 9.3 Each input can present a maximum of 20 Q of transistor width The output must drive a load equivalent to 100 Q of transistor width Choose transistor sizes to achieve this delay SOLUTION: The path electrical effort is H = 100/20 = and the branching effort is B = The design using NAND gates has a path logical effort of G = (4/3) × (4/3) = 16/9 and parasitic delay of P = + = The design using the AOI22 and inverter has a path logical effort of G = (6/3) × = and a parasitic delay of P = 12/3 + = Both designs have N = stages The path efforts F = GBH are 80/9 and 10, respectively The path delays are NF 1/N + P, or 10.0 Y and 11.3 Y, respectively Using compound gates does not always result in faster circuits; simple 2-input NAND gates can be quite fast To compute the sizes, we determine the best stage efforts, fˆ = F 1/ N = 3.0 and 3.2, respectively These are in the range of 2.4–6 so we know the efforts are reasonable and 9.2 331 Circuit Families the design would not improve too much by adding or removing stages The input capacitance of the second gate is determined by the capacitance transformation C in = i C out × g i i fˆ For the NAND design, C in = 100 Q × ( / 3) = 44 Q 3.0 For the AOI22 design, C in = 100 Q × (1) = 31 Q 3.2 The paths are shown in Figure 9.5 with transistor widths rounded to integer values 9.2.1.3 Input Ordering Delay Effect The logical A 10 B 10 effort and parasitic delay of different gate inputs 10 A are often different Some logic gates, like the B 22 10 22 AOI21 in the previous section, are inherently asymY 22 metric in that one input sees less capacitance than 10 D C 10 22 another Other gates, like NANDs and NORs, are C 10 nominally symmetric but actually have slightly difD ferent logical effort and parasitic delays for the dif10 ferent inputs Figure 9.6 shows a 2-input NAND gate annoFIGURE 9.5 Paths with transistor widths tated with diffusion parasitics Consider the falling output transition occurring when one input held a stable value and the other rises from to If input B rises last, node x will initially be at VDD – Vt ~ VDD because it was pulled up through the nMOS transistor on input A The Elmore delay is (R/2)(2C) + R(6C) = 7RC = 2.33 Y On the other hand, if input A rises last, node x will initially be at V because it was discharged through the nMOS transistor on input B No charge must be delivered to node x, so the Elmore delay is simply R(6C) = 6RC = Y In general, we define the outer input to be the input closer to the supply rail (e.g., B) and the inner input to be the input closer to the output (e.g., A) The parasitic delay is smallest when the inner input switches last because the intermediate nodes have already been discharged Therefore, if one signal is known to arrive later than the others, the gate is fastest when that signal is connected to the inner input Table 8.7 lists the logical effort and parasitic delay for each input of various NAND gates, confirming that the inner input has a lower parasitic delay The logical efforts are lower than initial estimates might predict because of velocity saturation Interestingly, the inner input has a slightly higher logical effort because the intermediate node x tends to rise and cause negative feedback when the inner input turns ON (see Exercise 9.5) [Sutherland99] This effect is seldom significant to the designer because the inner input remains faster over the range of fanouts used in reasonable circuits Recall that Y = 3RC is the delay of an inverter driving the gate of an identical inverter A 13 B C 13 D 13 21 A C 10 B D 13 A B 2x Y 6C 2C FIGURE 9.6 NAND gate delay estimation Y 332 Chapter A reset Combinational Circuit Design Y (a) A Y 4/3 reset (b) FIGURE 9.7 Resettable buffer optimized for data input 9.2.1.4 Asymmetric Gates When one input is far less critical than another, even nominally symmetric gates can be made asymmetric to favor the late input at the expense of the early one In a series network, this involves connecting the early input to the outer transistor and making the transistor wider so that it offers less series resistance when the critical input arrives In a parallel network, the early input is connected to a narrower transistor to reduce the parasitic capacitance For example, consider the path in Figure 9.7(a) Under ordinary conditions, the path acts as a buffer between A and Y When reset is asserted, the path forces the output low If reset only occurs under exceptional circumstances and can take place slowly, the circuit should be optimized for input-to-output delay at the expense of reset This can be done with the asymmetric NAND gate in Figure 9.7(b) The pulldown resistance is R/4 + R/(4/3) = R, so the gate still offers the same driver as a unit inverter However, the capacitance on input A is only 10/3, so the logical effort is 10/9 This is better than 4/3, which is normally associated with a NAND gate In the limit of an infinitely large reset transistor and unit-sized nMOS transistor for input A, the logical effort approaches 1, just like an inverter The improvement in logical effort of input A comes at the cost of much higher effort on the reset input Note that the pMOS transistor on the reset input is also shrunk This reduces its diffusion capacitance and parasitic delay at the expense of slower response to reset CMOS transistors are usually velocity saturated, and thus series transistors carry more current than the long-channel model would predict The current can be predicted by collapsing the series stack into an equivalent transistor, as discussed in Section 4.4.6.3 For asymmetric gates, the equivalent width is that of the inner (narrower) transistor The equivalent length increases by the sum of the reciprocals of the relative widths The relative current is computed using EQ (4.28), where N is the equivalent length Example 9.3 Size the nMOS transistors in the asymmetric NAND gate for unit pulldown current considering velocity saturation Make the noncritical transistor three times as wide as the critical transistor Assume VDD = 1.0 V and Vt = 0.3 V Use Ec L = 1.04 V for nMOS devices Estimate the logical effort of the gate SOLUTION: The equivalent length is + 1/3 = 4/3 times that of a unit transistor Apply2 A 1 B 1 Y FIGURE 9.8 Perfectly symmetric 2-input NAND gate ing EQ (4.28) gives a relative current of 0.83 Therefore, the transistors’ widths should be 1.20 and 3.60 to deliver unit current The logical effort is (1.20 + 2) / = 1.07, which is even better than predicted without velocity saturation In other circuits such as arbiters, we may wish to build gates that are perfectly symmetric so neither input is favored Figure 9.8 shows how to construct a symmetric NAND gate 9.2.1.5 Skewed Gates In other cases, one input transition is more important than the other In Section 2.5.2, we defined HI-skew gates to favor the rising output transition and LO-skew gates to favor the falling output transition This favoring can be done by decreasing the size of the noncritical transistor The logical efforts for the rising (up) and falling (down) transitions are called gu and gd, respectively, and are the ratio of the input capacitance of the skewed gate to the input capacitance of an unskewed inverter with equal drive for that transition Figure 9.9(a) shows how a HI-skew inverter is constructed by downsizing the nMOS 9.2 Circuit Families 333 transistor This maintains the same effective resistance for HI-skew Unskewed Inverter Unskewed Inverter Inverter (equal rise resistance) (equal fall resistance) the critical transition while reducing the input capacitance relative to the unskewed inverter of Figure 9.9(b), thus 2 reducing the logical effort on that critical transition to gu = A Y A Y A Y 2.5/3 = 5/6 Of course, the improvement comes at the 1/2 1/2 expense of the effort on the noncritical transition The logical effort for the falling transition is estimated by compar(a) (b) (c) ing the inverter to a smaller unskewed inverter with equal FIGURE 9.9 Logical effort calculation for HI-skew inverter pulldown current, shown in Figure 9.9(c), giving a logical effort of gd = 2.5/1.5 = 5/3 The degree of skewing (e.g., the ratio of effective resistance for the fast transition relative to the slow transition) impacts the logical efforts and noise margins; a factor of two is common Figure 9.10 catalogs HIskew and LO-skew gates with a skew factor of two Skewed gates are sometimes denoted with an H or an L on their symbol in a schematic Inverter NAND2 A Y gu = gd = gavg = A B 2 A Y 1/2 g u = 5/6 gd = 5/3 gavg = 5/4 B 1 LO-skew A Y gu = 4/3 gd = 2/3 gavg = B 1 B A gu = 5/3 gd = 5/3 gavg = 5/3 Y A 1/2 gu = gd = gavg = 3/2 Y A Y A B gu = 4/3 gd = 4/3 gavg = 4/3 Y HI-skew Y Unskewed NOR2 1/2 B A gu = 3/2 gd = gavg = 9/4 Y gu = gd = gavg = 3/2 1 FIGURE 9.10 Catalog of skewed gates Alternating HI-skew and LO-skew gates can be used when only one transition is important [Solomatnikov00] Skewed gates work particularly well with dynamic circuits, as we shall see in Section 9.2.4 9.2.1.6 P/N Ratios Notice in Figure 9.10 that the average logical effort of the LO-skew NOR2 is actually better than that of the unskewed gate The pMOS transistors in the unskewed gate are enormous in order to provide equal rise delay They contribute input capacitance for both transitions, while only helping the rising delay By accepting a slower rise delay, the pMOS transistors can be downsized to reduce input capacitance and average delay significantly In general, what is the best P/N ratio for logic gates (i.e., the ratio of pMOS to nMOS transistor width)? You can prove in Exercise 9.13 that the ratio giving lowest average delay is gu = gd = gavg = 3/2 334 Chapter Combinational Circuit Design the square root of the ratio that gives equal rise and fall delays For processes with a mobility ratio of Rn/Rp = as we have generally been assuming, the best ratios are shown in Figure 9.11 Inverter NAND2 Fastest P/N Ratio A 1.414 Y gu = 1.14 gd = 0.80 gavg = 0.97 NOR2 Y A B B A Y gu = 4/3 gd = 4/3 gavg = 4/3 1 gu = gd = gavg = 3/2 FIGURE 9.11 Gates with P/N ratios giving least delay Reducing the pMOS size from to ~ 1.4 for the inverter gives the theoretical fastest average delay, but this delay improvement is only 3% However, this significantly reduces the pMOS transistor area It also reduces input capacitance, which in turn reduces power consumption Unfortunately, it leads to unequal delay between the outputs Some paths can be slower than average if they trigger the worst edge of each gate Excessively slow rising outputs can also cause hot electron degradation And reducing the pMOS size also moves the switching point lower and reduces the inverter’s noise margin In summary, the P/N ratio of a library of cells should be chosen on the basis of area, power, and reliability, not average delay For NOR gates, reducing the size of the pMOS transistors significantly improves both delay and area In most standard cell libraries, the pitch of the cell determines the P/N ratio that can be achieved in any particular gate Ratios of 1.5–2 are commonly used for inverters 9.2.1.7 Multiple Threshold Voltages Some CMOS processes offer two or more threshold voltages Transistors with lower threshold voltages produce more ON current, but also leak exponentially more OFF current Libraries can provide both high- and low-threshold versions of gates The low-threshold gates can be used sparingly to reduce the delay of critical paths [Kumar94, Wei98] Skewed gates can use low-threshold devices on only the critical network of transistors VGG R Y Y Y 9.2.2 Ratioed Circuits Ratioed circuits depend on the proper size or resistance of devices for correct operation For example, in the 1970s and early 1980s before CMOS technologies matured, circuits were (a) (b) (c) often built with only nMOS transistors, as shown in Figure FIGURE 9.12 nMOS ratioed gates 9.12 Conceptually, the ratioed gate consists of an nMOS pulldown network and some pullup device called the static load When the pulldown network is OFF, the static load pulls the output to When the pulldown network turns ON, it fights the static load The static load must be weak enough that the output pulls down to an acceptable Hence, there is a ratio constraint between the static load and pulldown network Stronger static loads produce faster rising outputs, but increase VOL, degrade the noise margin, and burn more static power when the output should be Unlike complementary circuits, the ratio must be chosen so the circuit operates correctly despite any variations from nominal component values that may occur Inputs Inputs f Inputs f f 9.2 Circuit Families during manufacturing CMOS logic eventually displaced nMOS logic because the static power became unacceptable as the number of gates increased However, ratioed circuits are occasionally still useful in special applications A resistor is a simple static load, but large resistors consume a large layout area in typical MOS processes Another technique is to use an nMOS transistor with the gate tied to VGG If VGG = VDD, the nMOS transistor will only pull up to VDD – Vt Worse yet, the threshold is increased by the body effect Thus, using VGG > VDD was attractive To eliminate this extra supply voltage, some nMOS processes offered depletion mode transistors These transistors, indicated with the thick bar, are identical to ordinary enhancement mode transistors except that an extra ion implantation was performed to create a negative threshold voltage The depletion mode pullups have their gate wired to the source so Vgs = and the transistor is always weakly ON 9.2.2.1 Pseudo-nMOS Figure 9.13(a) shows a pseudo-nMOS inverter Neither high-value resistors nor depletion mode transistors are readily available as static loads in most CMOS Ids (+A) 1000 800 1.8 600 1.5 P = 24 Vin 1.2 400 Load P = 14 P 200 Ids 0.9 P=4 Vout 0.6 16 Vin 0.3 0.6 (b) (a) 0.9 1.2 1.5 1.8 Vout Ids (+A) 1.8 500 1.5 400 1.2 P = 24 P = 14 300 P = 24 Vout 0.9 200 0.6 P = 14 0.3 0 (c) P=4 100 P=4 0.3 0.6 0.9 Vin 1.2 1.5 1.8 (d) FIG 9.13 Pseudo-nMOS inverter and DC transfer characteristics 0.3 0.6 0.9 Vin 1.2 1.5 1.8 335 336 Chapter Combinational Circuit Design processes Instead, the static load is built from a single pMOS transistor that has its gate grounded so it is always ON The DC transfer characteristics are derived by finding Vout for which Idsn = |Idsp| for a given Vin, as shown in Figure 9.13(b–c) for a 180 nm process The beta ratio affects the shape of the transfer characteristics and the VOL of the inverter Larger relative pMOS transistor sizes offer faster rise times but less sharp transfer characteristics Figure 9.13(d) shows that when the nMOS transistor is turned on, a static DC current flows in the circuit Figure 9.14 shows several pseudo-nMOS logic gates The pulldown network is like that of an ordinary static gate, but the pullup network has been replaced with a single pMOS transistor that is grounded so it is always ON The pMOS transistor widths are selected to be about 1/4 the strength (i.e., 1/2 the effective width) of the nMOS pulldown network as a compromise between noise margin and speed; this best size is process-dependent, but is usually in the range of 1/3 to 1/6 Inverter 2/3 Y A 4/3 NAND2 gu = 4/3 gd = 4/9 gavg = 8/9 pu = 18/9 pd = 6/9 pavg = 12/9 2/3 Y A 8/3 B 8/3 NOR2 gu = 8/3 gd = 8/9 gavg = 16/9 pu = 30/9 pd = 10/9 pavg = 20/9 Generic 2/3 Y A 4/3 B 4/3 gu = 4/3 gd = 4/9 gavg = 8/9 pu = 30/9 pd = 10/9 pavg = 20/9 Y Inputs f FIGURE 9.14 Pseudo-nMOS logic gates To calculate the logical effort of pseudo-nMOS gates, suppose a complementary CMOS unit inverter delivers current I in both rising and falling transitions For the widths shown, the pMOS transistors produce I/3 and the nMOS networks produce 4I/3 The logical effort for each transition is computed as the ratio of the input capacitance to that of a complementary CMOS inverter with equal current for that transition For the falling transition, the pMOS transistor effectively fights the nMOS pulldown The output current is estimated as the pulldown current minus the pullup current, (4I/3 – I/3) = I Therefore, we will compare each gate to a unit inverter to calculate gd For example, the logical effort for a falling transition of the pseudo-nMOS inverter is the ratio of its input capacitance (4/3) to that of a unit complementary CMOS inverter (3), i.e., 4/9 gu is three times as great because the current is 1/3 as much The parasitic delay is also found by counting output capacitance and comparing it to an inverter with equal current For example, the pseudo-nMOS NOR has 10/3 units of diffusion capacitance as compared to for a unit-sized complementary CMOS inverter, so its parasitic delay pulling down is 10/9 The pullup current is 1/3 as great, so the parasitic delay pulling up is 10/3 As can be seen, pseudo-nMOS is slower on average than static CMOS for NAND structures However, pseudo-nMOS works well for NOR structures The logical effort is independent of the number of inputs in wide NORs, so pseudo-nMOS is useful for fast wide NOR gates or NOR-based structures like ROMs and PLAs when power permits 826 Index Inter-die process variation, 243 Interconnect, 211–239 circuit simulation, 319–322 crosstalk delay effects, 222–223 crosstalk noise effects, 223–224 defined, 211 effective resistance and Elmore delay, 227–229 impact on energy, 222–223 increasing circuit delay, 220–221 inductive effects, 224–227 Logical Effort limitations, 171 Logical Effort with wires, 236–237 overview of, 211 pitfalls and fallacies, 237–238 pitfalls of circuit simulation, 322 as process enhancement, 122–124 review and exercises, 238–239 scaling and, 257–259 variables effecting robustness, 243 wearout, 249–251 wire geometry, 211–213 Interconnect engineering, 229–236 crosstalk control, 232–234 low-swing signaling, 234–235 overview of, 229 regenerators, 236 repeaters, 230–232 width, spacing and layer, 229–230 Interconnect modeling, 213–220 capacitance, 215–217 inductance, 218–219 overview of, 213–215 skin effect, 219–220 Intermediate Frequency (IF) signal, software radio, 619–620 Internal circuit node, manufacturing test principle, 679 Internal variables, writing with HDLs, 706–707 International Electron Devices Meeting (IEDM), 137–138 International Technology Roadmap for Semiconductors (ITRS), 258 Intra-die process variation, 243 Intrinsic capacitance, 70 Intrinsic state, silicon, 99 Introduction circuit design, 42–45 CMOS fabrication and layout See fabrication and layout CMOS logic See CMOS logic design partitioning, 29–32 design verification, 53 fabrication, packaging and testing, 54–55 history, 1–6 logic design, 38–42 MIPS processor example, 33–38 MOS transistors, 6–8 physical design See Physical design preview, review and exercises, 55–59 Inversion region, MOS transistor, 61–62 Inverters See also FO4 (fanout-of-4) inverter delay choosing number to add for least delay, 166–169 CMOS, cross-section of, 19–20 cross-section of SOI, 361 DC transfer for static CMOS, 88–89 fabrication process, 20–24 gate layouts for, 27 as repeaters, 230–231 as static CMOS logic gate, 9–11 transient analysis using SPICE, 292–294 Inverters, tristate, 15–16 Ion implantation, 23–24, 104 IP (intellectual property) blocks, 621, 654–655 IQ modulator, radio transmitter applying hierarchy, 622 applying regularity, 624–625 software radio design, 618–619 IR drops overview of, 557–558 power supply noise caused by, 356–357 preventing in high-power architectures, 556 IR (infrared) imaging, probing hot spots, 674 Isolated polysilicon lines, 267–268 Isolated regions, of contacted diffusion, 70 Isolation, CMOS technology, 106–107 Isolation transistors, 512 Itanium sequencing methodology, case study, 423 Iterative solutions for sizing, 171–173 ITRS (International Technology Roadmap for Semiconductors), 258 Jamb latches, 393 Jitter, 267 Jitter clock skew sources, 568, 578 Johnson counter, 466 Junction grading coefficient, 72 Junction leakage as nonideal I-V effect, 80 overview of, 84–85 as source of static power, 196–197 Junction temperatures, 242–243 Junctions building deep using deposition, 104 building silicon semiconductor, 99 K = A + B comparator, 463–464 Keeper circuit, 343–345 Kilby, Jack, 1–2 Kill, single-bit addition, 430–434 Kill value (logical and arithmetic shifts), 472 Klass Semidynamic Flip-flop (SDFF), 399 Knowles tree, 449–450, 456–458 Kogge-Stone tree comparison of adder architectures, 456–458 flagged prefix adders using, 460 higher-valency tree adders using, 450–452 overview of, 448–450 sparse tree adders using, 453–454 L di/dt noise, 558–559 L-model wire, 213 L2L (lot-to-lot ) process variations, 243 Ladner-Fischer tree comparison of adder architectures, 456–458 overview of, 449–450 sparse tree adders using, 453 Lambda design rules, 136 Land Grid Array (LGA) packages, 550–552 Large-scale integration (LSI) circuits, Large-signal (single-ended) bitline sensing, 511–512 Large SRAMs, 515–517 Laser Voltage Probing (LVP), silicon debugging, 674 Last In First Out (LIFO) queues, 535 Latches defined, 375 metastable state in, 412–415 as sequencing element, 16–18 writing sequential logic with HDLs, 721–722 Latches, in circuit design conventional CMOS, 392–393 enabled, 397–398 incorporating logic into, 398–399 pulsed, 395–396 radiation-hardened, 402 resettable, 396–397 sequencing static circuits See static circuits, sequencing time borrowing, 386–389 True Single-phase Clock (TSPC), 402 Latchup, as reliability problem, 253–254 Lateral diffusion, 23–24 Lateral scaling, 255–256 Lattice, silicon, 6–7 Layers density rules for manufacturing, 134 interconnect design using, 260 interconnect engineering and, 229–230 Layout See also Fabrication and layout automated layout generation, 641–644 custom mask, 634 decoder, 507–508 full adder, 433–434 gate, 27–28 high-speed clock distribution networks, 575 statistical analysis of variability of, 269 symbolic, 634 timing optimization at level of, 143 typical standard cell, 633 verifying using design rule checker, 53 Layout dependence of capacitance, RC delay model, 153–154 Layout generation (physical synthesis), design flow, 637, 641–644 Layout (or design) rules contact rules, 114–115 introduction to, 24–26 metal rules, 115–116 micron design rules, 118–119 MOSIS scalable CMOS, 117–118 other rules, 116 overview of, 113 pitfalls of waiving, 136 scribe line and other structures, 116–117 summary, 116 transistor rules, 114 via rules, 116 well rules, 113–114 Layout versus schematic (LVS), 53, 646 LCR (leakage current replica) keeper, 345 LDD (lightly doped drain), 108–110 Leakage, 80–85 controlling in dynamic circuits, 343–345 Index controlling in low-power SRAMs, 518–519 controlling problem of subthreshold, 129–130 controlling with clock gating, 208 domino noise budget example of, 359 gate, 82–84 impact of scaling on, 261 impact of variation on, 271–272 junction, 84–85 as nonideal I-V behavior, 87 overview of, 80–81 as pitfall of circuits, 356 pitfall of ignoring, 94, 206 power dissipation through, 195 stress-induced leakage current, 248–249 subthreshold, 81–82 Leakage current replica (LCR) keeper, 345 Lean Integration with Pass Transistors (LEAP), 352–353 LEAP (Lean Integration with Pass Transistors), 352–353 LER (line edge roughness), channel length variance, 267–268 Level models, SPICE circuit simulation, 299 Level and models, SPICE circuit simulation, 300 Level-converter flip-flops, 408–409 Level converters, 190–191, 408–409 LF (loop filter) DLL, 589 global clock generators, 569 PPL, 586 LGA (Land Grid Array) packages, 550–552 lib statement, 302 Library of gates, 41, 633 library use clause, VHDL code, 700–701 LIFO (Last In First Out ) queues, 535 Lightly doped drain (LDD), 108–110 Line edge roughness (LER), channel length variance, 267–268 Linear delay model, 155–163 delay in logic gate, 158–159 drive, 159 extracting logical effort from datasheets, 159–160 limitations, 160–163, 171 logical effort, 156 overview of, 155 parasitic delay, 156–158 Linear extrapolation threshold voltage extraction, 307 Linear-feedback shift register (LFSR), 466–467, 685 Linear region of operation detailed MOS gate capacitance model, 70–71 MOS transistor, 62–63 MOS transistor with long channel, 64–68 Liner oxide, 107 Ling adder, 454–457 Literals, PLAs, 537 Lithographically friendly 6T SRAM cell, 504–505 LO-skew gates, 332–333 Load board, as test fixture, 666–668 Load, defined, 142 Local bitlines, 511–512 Local clock gaters, 566, 575–577 Local interconnect, 111 Local Oscillator (LO), software radio, 619–620 Local Oxidation of Silicon (LOCOS) processes, 106 Local voltage dithering, 192 Local wires, interconnect scaling, 257–258 Local wordlines, SRAMs, 508 Locality in hardware and software design, 627 in structured design, 31, 626–627 Lock choppers, 395–396 LOCOS (Local Oxidation of Silicon) processes, 106 Log-normal distribution, random variables, 266 Logarithmic adders See Tree adders Logarithmic shifters, 472 Logic abstraction, 616 See also Structured design strategies analyzers, 663–664, 668, 686 CMOS See CMOS logic fault tolerance, 276–277 incorporating into latches, 398–399 Logic design, 38–42 defining block diagrams, 38–40 defining top-level interfaces, 38 floorplanning influencing, 45 hardware description languages, 40–42 hierarchy, 40 overview of, 30, 38 Logic gates applying linear delay model to, 158–159 designing adders using, 431 equivalent RC circuits and, 147–148 finding DC transfer characteristics/noise margins of, 315 history of, Logic level, 143, 493–494 Logic simulators, 41, 287 Logic synthesis tools, 41, 457–458 logic type, standard Verilog, 740 logic type, SystemVerilog, 700–701 Logic verification defined, 659 MIPS processor example, 665 overview of, 660–662 principles, 670–673 Logical clocks, 566 Logical effort computing Elmore delay, 153 extracting from datasheets, 159–160 in linear delay model, 155, 156 measuring for each input of gate, 315–318 notation for, 170 of transmission gate circuit, 352 with wires, 236–237 Logical effort of paths, 163–173 choosing number of stages, 166–169 delay in multistage logic networks, 163–166 in dynamic circuits, 346–347 estimating delay of static RAM/register files, 520–522 limitations of, 171 notation for, 170 sizing, 171–173 summary and observations, 169–171 827 Logical shifts, 472–476 Logos, pitfalls of placing on chip, 136 Long-channel I-V, 64–68 See also I-V (current and voltage), nonideal behavior of Long-channel regime, 77 Lookahead adders See Tree adders Loop dynamics DLL, 589 PPL, 586–587 Loop filter See LF (loop filter) Lot-to-lot (L2L) process variations, 243 Low-k dialectrics, 123–124, 211–212 LOW noise margin, 91–92 Low power architectures energy scavenging for, 565–566 microarchitectures, 204 on-chip power distribution network in, 556 overview of, 204–206 parallelism and pipelining, 204–205 power management modes, 205–206 reducing dependence on fossil fuels, 181 Low-power SRAMs, 517–520 Low-swing signaling system, 234–235 LSFR (linear-feedback shift register), 466–467, 685 LSI (large-scale integration) circuits, LVP (Laser Voltage Probing), silicon debugging, 674 LVS (layout versus schematic), 53, 646 Machine language, 34 Macro substitution, 646 Magnetic fields, in inductance, 218 Magnitude comparator, 462 Majority carriers, MOS transistors as, 61 Majority gates, 431 Manchester carry chain carry-skip adder stage, 443 MODL design, 347 online reference for, 441 Manufacturability, design for, 646, 687–688 Manufacturing CMOS processing technology issues, 133– 135 costs of prototype, 648–649 failures, 675 variables affecting robustness, 241–246, 269–270 Manufacturing test principles, 676–681 Automatic Test Pattern Generation, 680 controllability, 679 delay fault testing, 680–681 fault coverage, 680 fault models, 677–679 observability, 679 purpose of manufacturing test, 676–677 repeatability, 679 survivability, 679–680 Manufacturing tests, 659, 664–665 Market, semiconductor, 1–2 Mask database, 130, 132–133 Mask descriptions, chip design, 54 Mask-programmed ROMs, 127, 530 Masks contact rules, 115 defining wells by separate, 105 metal rules, 116 828 Index in photolithography process, 101–103 scribe line rules, 117 transistor rules, 114 via rules, 116 well design rules, 114 Master-checker configuration, fault tolerance, 276 Masuoka, Fujio, 531 Matched delays, variation effecting, 273–274 Matching, CAM, 535–536 Matchlines, CAM, 535–536 Max-delay constraints, 379–383, 640 Max-time, 142 Maximal-length shift register, 467 Maximum of random variables, 265–266 MCF (Miller Coupling Factor), 222 Mealy FSM machines, 735 Mean time between failures (MTBF), and reliability, 247 Meander structure, 124 measure statement, SPICE, 295, 319 Measurement, subcircuit, 294–296 Medium-scale integration (MSI), 4, 633 Mega electron volt levels (MeV), 104 Megahertz Wars, 282 Memory fault tolerance and, 275–277 multiplexers and, 15–16 power of density of logic vs., 204 sequential circuits and, 16 writing with HDLs, 745–749 Memory BIST, 686 Memory elements, 375 MEMS (microelectromechanical systems), 128 Metal choosing orientation of, 48 design rules, 115–116 parasitic effects of metal fill, 136 standard cells and, 48 wire geometry and, 211–213 Metal gates, challenges of, 121 Metal Oxide Semiconductor Field Effect Transistors See MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) Metal-Oxide-Semiconductor transistors See MOS transistors Metal slotting rules, 135 Metal to n-active contact, 114–115 Metal to p-active contact, 114–115 Metal to polysilicon contact, 115 Metal to well or substrate contact, 115 Metallization, 110–112 Metastability mistakes made with synchronizers, 418 sequencing element delays and, 406 synchronizers and, 412–415 Metrology, 112–113 MeV (mega electron volt levels), 104 Microarchitectures floorplanning influencing, 45 implementing multicycle MIPS, 34–38 overview of, 30 reducing power consumption with, 204 timing optimization for, 143 Microbatteries, 566 Microelectromechanical systems (MEMS), 128 Micron design rules, 118–119 Microprocessors comparing CMOS design methods, 636 custom-designed, 635 platform-based, 635–636 solving system design problem with, 627–628 using programmable logic vs., 628 Microstrips, 126 Miller Coupling Factor (MCF), 222 Miller effect, 163 Min-delay constraints between flip-flops, 394–395 sequencing static circuits, 383–386 timing analyzer checking for, 640 Min-time, 142 minimum energy, 200–203 minimum energy delay-product, 203 minimum energy under delay constraint, 203–204 Minority carrier injection effect, 357–359 Minterms, PLAs, 537 MIPS processor example, 33–38 MIPS architecture, 33–34 multicycle MIPS microarchitectures, 34–38 overview of, 33 testing, 665–666 MIPS processor example, HDLs, 755–775 defined, 755 SystemVerilog, 757–765 testbench, 756 VHDL, 766–775 Mirror adders, 431–432, 434 Mismatches, modeling between currents, 319 Miss signal, CAMs, 536 Mixed-signal (or custom-design) flow overview of, 645–646 substrate noise problem in, 565 Mobility defined, 66 enhancing CMOS process with higher, 121 Mobility degradation, 74–78 Mobility ratio, 67 Mobius counter, 466 ModelSim logic simulator, 287 Modified Baugh-Wooley multiplier, 479–480 Modified Booth encoding, 481 MODL (multiple-output domino logic), 347–348 Modularity defined, 18 hardware and software design, 627 mixed-signal or custom-design flow, 646 structured design, 31, 625–626 Modules, defined in Verilog, 41 Modules, writing with HDLs modeling testbenches, 749–754 overview of, 700–701 writing parameterized, 742–745 Modulo 2n – addition operation, flagged prefix adder, 460 Moment matching technique, CAD, 228 Monotonically rising, 341 Monotonicity, 341 Monte Carlo simulations assessing impact of variations, 269 finding effects of random variations on circuit, 319 for process spread, 688 SRAM cell stability, 503 Moore FSM machines, 735 Moore’s Law, 3–6 MOS transistors, 61–97 C-V characteristics, 68–73 creating, 6–8 DC transfer characteristics, 87–93 introduction, 61–64 long-channel I-V characteristics, 64–68 nonideal I-V effects See I-V (current and voltage), nonideal behavior of pitfalls and fallacies, 93–94 review and exercises, 94–97 MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) CMOS technology and, high-voltage, 122 historical perspective, 207 overview of, MOSIS layout design rules, 25–26 mask descriptions, 54 scalable CMOS design rules, 117–118 MRCMOS (Multiple Threshold CMOS), 198 MSI (medium-scale integration), 4, 633 MTBF (mean time between failures), and reliability, 247 Multicycle MIPS microarchitectures, 34–38 Multilevel Flash cells, 532 Multilevel-lookahead adders See Tree adders Multiple bank design, 515 Multiple-input addition, datapaths, 458–459 Multiple-output domino logic (MODL), 347–348 Multiple registers, 720–721 Multiple Threshold CMOS (MTCMOS), 198 Multiple threshold voltages, 199, 334 Multiplexers CMOS, 15–16 creating enabled latches and flip-flops, 397–398 transmission gate full adders forming, 434 Multiplexing, column circuitry in DRAMs, 525–526 Multiplication, datapaths, 476–485 booth encoding accelerating, 480–485 column addition, 485–489 final addition, 489–490 fused multiply-add, 490 hybrid, 489 overview of, 476–477 serial, 490 summary, 490 two’s complement array, 479–480 unsigned array, 478–479 Multiported SRAMs, and register files, 514–515 Multiprocessor, software radio as, 624–625 Multistage logic networks, delay in, 163–166 Mutual inductive coupling, 227 Mux-latch, 399 N-bit adders, 434–436 n-diffusion, fabrication, 23–24 n-select mask, CMOS transistors, 114 Index n-type semiconductors, 6–7 n-type transistors See nMOS transistors n-well process CMOS technology, 103 design rules, 25–26, 113–114 fabrication process, 21–24 gate layouts, 27 inverter cross-section with, 19–20 well structure in triple-well process, 104–105 Naffziger pulsed latch, 396 NAND Flash memories, 531 NAND gates asymmetric, 332 bubble pushing using, 329 CMOS, input ordering delay effect, 331 layouts, 27–28 measuring logical effort of, 156 predecoding technique, 507–508 as static CMOS logic gate, 9–11 NAND operation, 468 NAND ROMs, 530–531 Nanotechnology, and leakage, 195 Nanotechnology, future of, 130 Nanotubes, 130 Narrow channel effect, 80 NBTI (negative bias temperature instability), oxide wearout, 248 NCO (Numerically Controller Oscillator), 622–624 Negative bias temperature instability (NBTI), oxide wearout, 248 Negative-edge triggered flip-flops, 18–19 Negative photoresist, 101 Negative slack, 142 Negative temperature coefficient, 85 Nested polysilicon lines, channel length variance, 267–268 Netbooks, 283 Netlists, 43–44, 754–755 nMOS transistors architecture, characteristics of ideal, 67–68 CMOS compound gates, 11–12 CMOS inverter, CMOS logic gates, 9–11 CMOS NAND gate, CMOS NOR gate, 11 CMOS technology and, DC transfer for static CMOS inverter, 88–89 development of, historical perspective, 207 modes of operation, 61–63 pass transistors and transmission gates, 12–14 pitfalls of pass, 94 well structure in triple-well process, 104–105 Width/Length ratio of, 26–27 Noise automated layout analysis, 644 in crosstalk, 223–224 diffusion input sensitivity of circuits, 358 domino noise budget, 359–360 reducing on dual-rail busses, 343 substrate, 565 using power supply filtering for, 564 Noise feedthrough (or propagated noise), 92, 360 Noise margins (or noise immunity) addressing in dynamic circuits with keepers, 343–345 DC transfer characteristics, 91–92 determining, 343–345 finding for logic gates, 315 Nominal (typical) variables, 244–246 Non-recurring engineering cost See NRE (non-recurring engineering cost) Nonblocking assignments, HDLs, 717, 731–734 Nonideal I-V effects See I-V (current and voltage), nonideal behavior of Nonlinear delay model, 174 Nonrestoring circuit, tristate buffer, 14 Nonsaturated mode of operation, 63 Nonvolatile memory See NVM (nonvolatile memory) NOR gates bubble pushing using, 329 CMOS, 11 dynamic decoders and, 509–510 ganged CMOS and, 338 input ordering delay effect, 331 measuring logical effort of, 156 NOR operation, 468, 537–539 NOR ROMs, 527, 530 NOR structure, PLA, 628–629 NORA (NO RAce) Domino, 348–349 NORA (NO RAce) technique, 394 Normal distributions, modeling variations as, 242 Normal random variables behavior of maximum, 265–266 exponential of, 266 overview of, 264–265 sums of, 264–265 NOT gate, NP Domino, 348–349 npn bipolar transistors, 126 NRE (non-recurring engineering cost) comparing CMOS design methods, 636 cost of chip and, 56 design economics of, 647–649 using gate arrays to contain, 631–632 Numbers, writing with HDLs, 708–709 Numerical apertures, photolithography, 102 Numerically Controller Oscillator (NCO), 622–624 NVM (nonvolatile memory) overview of, 127–128 ROM as, 527–529 vs volatile, 497 Off-axis illumination, photolithography, 103 OFF current, variation of, 270 OFF transistors CMOS inverter, CMOS logic See CMOS logic long-channel model, 65 MOS transistors as, 8, 62–63 sources of leakage in, 74–75 On-chip bypass capacitance overview of, 559–560 829 power distribution system model, 565 power supply impedance and, 561–562 power supply step resistance and, 562–563 On-chip power distribution network, 556–557 ON current CMOS logic See CMOS logic impact of variation on, 270 MOS transistors as, ON transistors CMOS inverter, long-channel model, 65 mobility effect dominating, 75 MOS transistor, 62–63 One-shots, 395–396 One-time programmable (OTP) memory, 127, 530 One/zero detectors, datapaths, 461–462 Online references boundary scan operations, 689 building simple MIPS microprocessor, 33 CMOS physical design styles, 656 designing own microprocessor chip, Domino implementation issues, 456 Manchester carry chain adder, 441 optional topics for this book, 56 Pentium 4/Itanium sequencing methodologies, case study, 423 scan design, 684 sequencing dynamic circuits, 411 serial multiplication, 490 timing analysis delay models, 173 True Single-phase Clock (TSPC) latches and flip-flops, 402 two-phase timing types, 411 Opaque latches, for sequential circuits, 16 OPC (optical proximity correction), photolithography, 103 Open bitlines, DRAM, 524 Open Circuit fault model, 677–678 Operands, writing HDL, 702, 703 Operating mode, basing voltage on, 190 Operators, HDL concatenation, 711 precedence, 708 SystemVerilog, 702 VHDL, 703 Opportunistic time borrowing, 389 Optical proximity correction (OPC), photolithography, 103 optimization capabilities, HSPICE, 296–298 option post command, SPICE, 292 option scale settings, 301, 324 OR function, 329–331 OR operation, 468 OR plane, PLAs, 537–539, 628 Orientation effect, channel lengths, 267 Oscillator, PPL, 582–583 Oscilloscopes, 686 others clause, VHDL, 728 OTP (one-time programmable memory), 127, 530 output See I/O (input/output) Output loading, in circuit simulation, 323 Output slope, linear delay model error, 161 Overglass cuts (or passivation), 112 Overlap, 113, 118 Overlap capacitances, 70 830 Index Overvoltage failure, 252–253 Oxidation in fabrication process, 22–23 of silicon, 106 Oxide thickness controlling leakage in low-power SRAMs, 518–519 static power and, 197 statistical analysis of variability, 269 Oxide wearout hot carriers creating, 248 overvoltage creating, 252 as reliability problem, 247–248 time-dependent dielectric breakdown causing, 248–249 Oxides, gate, 83, 119–120 Oxynitride gate dielectrics, 120 Oxynitrided oxide, 108 p-diffusion, fabrication process, 23–25 P/N ratios, logic gates, 333–334 p-select mask, CMOS transistors, 114 p-type, 99 P-type semiconductors, P-type transistors See pMOS transistors p-well process CMOS technology, 103 design rules, 114 in gate and shallow source/drain definition, 109 well structure in triple-well process, 104–105 P6 architecture, 281–282 Package diagrams, 656 Package parasitics, 552 Packages in power distribution system model, 564–565 of processed wafers, 55 Packaging and cooling, 549–555 chip-to-package connections, 551–552 common integrated circuit packages, 549–551 heat dissipation, 552–553 package parasitics, 552 properties of ideal packages, 549 temperature sensors, 553–555 Pad frame, 46–47, 551 Pad-limited chips, 47, 551 Pad oxide, 107 Parallel hierarchy, structured design, 620–621 Parallel In Serial Out (PISO) memory, 533–534 Parallel plate capacitance, 215 Parallel-prefix adders See Tree adders Parallel-prefix computations, 491–493 Parallel scans, 683–684 Parallelism, reducing power consumption, 204–205 param statement, HSPICE, 293–294 parameter statement, SystemVerilog, 742–745 Parameterized modules, writing with HDLs, 742–745 Parametric yield, 267 Parasitic capacitance applying Logical Effort with wires, 236 computing Elmore delay, 151–152 defined, 64, 72 for delay estimation, 308–310 Parasitic capacitors, 69 Parasitic delay computing Elmore delay, 153 computing Logical Effort of paths, 164–166 of dynamic gates, 341 extracting logical effort from datasheets, 159–160 in linear delay model, 155–158 Logical Effort notation for, 170 measuring for each input of gate, 315–318 ratioed circuits and, 336 Parasitic estimator tools, 319–320 Parasitic extraction automated layout, 643 mixed-signal or custom-design flow, 646 pitfalls of inaccurate, 657 Parasitics, package, 552 Parity, as error-detecting code, 468 Parity-check matrix, 469–470 Partial products for Booth encoded multiplier, 481–484 comparing XOR levels in multiplier trees, 489 for two's complement multiplier, 479–480 Partial write operation, column multiplexing, 514 Partially depleted (PD) SOI devices, 361–364 Partovi pulsed latch, 396, 399 Pass-gate leakage, SOI circuit, 363 Pass gates See Transmission gates Pass-transistor circuits, 349–354 Complementary Pass Transistor Logic, 352–353 Lean Integration with Pass Transistors, 352–353 mixing CMOS with transmission gates, 351–352 other families of, 353–354 overview of, 349–351 Pass transistors DC characteristics, 92–93 historical perspective, 369 pitfall of ignoring driver resistance in, 367 pitfall of using nMOS, 94 transmission gates and, 12–14 Passivation (or overglass cuts), 112 Paths computing logical effort of See Logical effort of paths pitfalls of circuit simulation, 323 simulating, 313–315 Pattern-dependent gate leakage, 196 Patterns fabrication process, 22 test program, 668–669 PBRS (pseudo-random bit sequence), 467 PC (program counter), multicycle MIPS microarchitectures, 36 PD (partially depleted) SOI devices, 361–364 PDF (probability distribution function), 263 PDP (power-delay product), 200–201, 206 PDs (phase detectors) DLL, 589 global clock generators using, 569 PPL, 584–586 Pelgrom's model, 267–269 Pentium Processor, 282 Pentium sequencing methodology, case study, 423 The Pentium Chronicles (Colwell), 282 Pentium II Processor, 281 Pentium III Processor, 281–282 Pentium Pro Processor, 281 Pentium Processor, 280–281 Performance dealing with expected, 695–696 design rules and, 113 impact of scaling on, 258 making outrageous claims about, 367 Perpetrator, crosstalk noise, 223–224 Personpower, design economics, 653 PG carry-ripple addition, 438–441 PG logic carry generation and propagation, 437–438 carry lookahead adder, 443–444 carry-ripple adder, 438–441 carry-skip adder, 441–442 PGA (Pin Grid Array) packages, 550–551 Phase, 589 phase detectors, DLL See PDs (phase detectors) Phase-locked loops See PPLs (phase-locked loops) Phase shift masks (PSMs), photolithography, 103 Phonon scattering, 120–121 Photolithography, 20–21, 101–103 Photomask (or reticle), in photolithography, 101 Photoresists (PRs), 22–23, 101–103 Physical clocks clock skew and, 566–567 creating clock skew budget, 568 defined, 566 local clock gaters receiving, 575–577 Physical design, 45–53 area estimation, 51–53 arrays, 51 CMOS styles, 656 design for manufacturability, 688 floorplanning, 45–48 overview of, 30 pitch matching, 50 slice plans, 50–51 standard cells, 48–49 Physical domain defined, 615 in design partitioning, 31–32 functional equivalence at abstraction levels, 660–661 levels of design abstraction for, 615–616 structured design for See Structured design strategies Physical limits, to scaling, 262 Physical synthesis (or layout generation), design flow, 637, 641–644 PICA (Picosecond Imaging Circuit Analysis), silicon debugging, 674 Picosecond Imaging Circuit Analysis (PICA), silicon debugging, 674 Piecewise linear (PWL) source, SPICE, 290 Piezoelectric microgenerators, 566 Pin Grid Array (PGA) packages, 550–551 Index Pinched off, MOS transistor saturation, 63 Pinout section, data sheets, 655 PIP (poly-insulator-poly) capacitor, 124 Pipelines difficulties of using pulsed latches in, 404 wave, 420–422 Pipelining, reducing power consumption, 204–205 Pirana etch, fabrication process, 23–24, 111 PISO (Parallel In Serial Out), 533–534 PISO (Parallel In Serial Out) memory, 533–534 Pitch matching, for snap-together cells, 50 Pitch, track, 28 Pitch, wire, 211 Placement of cells, automated layout, 641–644 PLAs (Programmable Logic Arrays) defined, 497 overview of, 537–541 physical design, 50–51 programmable logic devices based on, 628 Plasma-induced gate-oxide damage (or antenna effect), 133 Plastic Leadless Chip Carrier (PLCC) package, 550–551 Plastic transistors, 122 Platform-based design, 635–636 PLCC (Plastic Leadless Chip Carrier) package, 550–551 plot command, SPICE, 291–292 pMOS transistors characteristics of ideal, 67–68 CMOS compound gates of, 11–12 CMOS inverter of, CMOS logic gates of, 9–11 CMOS NAND gates of, CMOS NOR gates of, 11 CMOS technology and, DC transfer for static CMOS inverter of, 88–89 development of, modes of operation, 63 MOS transistor architecture and, pass transistors and transmission gates of, 12–14 well structure in triple-well process of, 104–105 Width/Length ratio of, 26–27 pnp bipolar transistors, 126 Point contact transistors, 1–2 Poisson distribution, 270 Poly-insulator-poly (PIP) capacitor, 124 Polycide process, 109–110 Polysilicon mask, CMOS transistors, 114 Polysilicon (polycrystalline silicon) fabricating transistor gates, 23–24 in gate and shallow source/drain definition, 108–110 MOS transistor architecture, Ports accessing memory cells via, 498 debugging, 663 modeling multiported register files in HDL, 747–748 multiported SRAMs and register files, 514–515 Positive-edge triggered flip-flops, 18–19 Positive photoresist, 101 Positive slack, 142 Posynomials, 171 Power, 181–210 comparing adder architectures for, 457 definitions, 182 designing for manufacturability, 688 dynamic See Dynamic power energy-delay optimization and, 200–204 examples, 182–184 extracting gate capacitance for estimating, 308 historical perspective, 207–208, 278 impacted by scaling, 261 low power architectures, 204–206, 517–520 measuring consumption of, 318–319 overview of, 181–182 pitfalls and fallacies, 206 review and exercises, 209–210 sources of dissipation of, 184–185 SRAM and, 520–522 static power, 194–200 Power analysis automated layout generation, 644 design flow, 641 mixed-signal or custom-design flow, 646 Power-delay product (PDP), 200–201, 206 Power distribution subsystem, 555–566 charge pumps, 564–565 energy scavenging, 565–566 IR drops, 557–558 L di/dt noise, 558–559 on-chip bypass capacitance, 559–560 on-chip power distribution network, 556–557 overview of, 555–556 power network modeling, 560–564 power supply filtering, 564 substrate noise, 565 Power gating controlling leakage in low-power SRAMs, 519 designing, 198 example, 198–199 overview of, 197–198 reducing power consumption with, 205 Power grid, pitfalls of leaving gaps in, 238 Power management modes, low power architectures, 205–206 Power network modeling distributed power supply models, 563–564 overview of, 560–561 power supply impedance, 561–562 power supply step response, 562–563 Power supply analysis, testing, 691–692 distributed models, 563–564 filtering, 564 impedance, 561–562 step response, 562–563 Power supply noise effect, 356–357, 359–360 PPL (Push-Pull Transistor Logic), 353–354 PPLs (phase-locked loops), 580–587 advanced architectures, 587 bandwidth and stability, 570 clock skew from, 578 clock system architecture, 568 defined, 580 divider, 583–584 DLLs vs., 570 frequency multiplication with, 570–571 global clock generators using, 569–570 loop dynamics, 586–587 loop filter, 586 oscillator, 582–583 overview of, 580–581 phase detectors, 584–586 using power supply filter on, 564 validation, 587 Precedence, HDL operator, 708 Precharge mode, dynamic circuits, 339–340 Predecoding circuits, SRAM row circuitry, 507–509 Prefix adders, sparse tree adders, 451–452 Prefix computation, 437–438 Prefix operator, 437–438 Prescaler counter, 465 Principles of Operation manuals, 656 print statement, SPICE, 291–292 Printed circuit board, 666 Printed circuit board with chip in situ, 666 Priority encoder, parallel-prefix computations, 491 Probability distribution function (PDF), 263 Probability, switching, 187–188 Probe cards, 666–668 Probe points, silicon debugging, 673 Process characteristics, 313–314 Process check structures, 117 Process corner effects, 360 Process generations (technology node), 4–5 Process sensitivity, in circuits, 358–359 Process simulators, 287 Process spread, designing for, 688 process statements, VHDL, 718–722, 750–754 Process tilt, 244 Process variation affecting domino keepers, 345 classifying, 243–244 defining design corners, 244–246 effects on robustness, 243 Process, Voltage, and Temperature (PVT) variation sources, 242 831 832 Index Processes, characteristics of CMOS, 311–313 Processing technology See CMOS processing technology Productivity, impact of scaling on, 261–262 Products, PLAs, 537 program counter (PC), multicycle MIPS microarchitectures, 36 Programmable logic, 628–631 Programmable Logic Arrays See PLAs (Programmable Logic Arrays) Programmable ROM (PROM), 498, 529–530 Programming languages, HDLs vs., 699 Project management, design economics, 653–654 Projection printing, 101 PROM (Programmable ROM), 498, 529–530 Propagate, in single-bit addition, 430–434 Propagated noise, 92, 360 Propagation delay characterizing sequencing element delays using, 405–408 computing using transient response, 145 definition of, 141–142 metastable state and latch, 414–415 Properties of ideal packages, 549 of ideal power distribution networks, 55 of random variables, 263–266 SRAM, 498–499 Prototype manufacturing costs, design economics, 648–649, 653–654 Proximity effect, channel lengths, 267 Proximity printing, 101 PRs (photoresists), 22–23, 101–103 PRSG (pseudo-random sequence generator), 684–685 Pseudo-random bit sequence (PBRS), 467 Pseudo-random sequence generator (PRSG), 684–685 Pseudogenerate (pseudo-carry) signals, Ling adder, 454–456 Pseudopropagate signals, Ling adder, 454–456 PSMs (phase shift masks), photolithography, 103 PSPICE, 288 Pull-down networks, CMOS gates Cascode Voltage Switch Logic using, 339 CMOS logic, 9–11 ratioed circuits and, 334–338 Pull-up networks, CMOS gates, 9–11, 334–338 Pulse generators, 395–396 Pulse sources, SPICE, 290–291 Pulsed latches with adaptive sequencing elements, 411 choosing for static sequencing element, 403 Klass Semidynamic Flip-flop similar to, 399 sequencing element delays, 407 sequencing with, 395–396 Punchthrough problems, from overvoltage, 252 Push-Pull Transistor Logic (PPL), 353–354 PVT (Process, Voltage, and Temperature) variation sources, 242 PWL (piecewise linear source), SPICE, 290 Quadrature Phase Shift Keying (QPSK) modulation, software radios, 619 Queues, 533–535 Race conditions, 383–386, 394 Radiation-hardening, 401–402, 543–544 Radio-frequency identification (RFID) tags, 566 Radio frequency (RF) applications, 122, 618–621 Radix-2 (or valency-2) prefix networks, 438–439, 456–458 Rail-to-rail drivers, 234 Rail-to-rail output, 392 Rails, 12–13 RAM (random access memory), 497, 745–747 Random access memory (RAM), 497, 745–747 Random access scan, 683 Random clock skew sources, 568, 578 Random logic, 48 Random test vectors, 671 Random variables, properties of, 263–266 Random variations, 267, 319 Rapid prototyping approach, 653 Ratio failures, in circuits, 355 Ratioed circuits dynamic circuits circumventing drawbacks of, 339 historical perspective, 367–368 not working well at low voltage, 366 overview of, 334–338 Razor flip-flops, 410–411 RAZOR II pulsed latches, 411 Razor latches, 402 RBB (reverse body bias), 199–200 RC delay model, 146–155 effective resistance, 146–147, 154–155 Elmore delay, 150–153 equivalent RC circuits, 147–148 estimating parasitic delay of gate, 156–157 gate and diffusion capacitance, 147 layout dependence of capacitance, 153–154 transient response, 148–150 Read assist techniques, low-power SRAMs, 518 Read margin, SRAM cells, 502–503, 505–506 Read-only memory See ROM (read-only memory) Read operation, SRAM cells, 500–502 Read ports, multi-ported RAM and, 514–515 $readmemb, SystemVerilog, 753 $readmemh, SystemVerilog, 753 Receive path, software radio, 620 Rectangular-diffusion cell, SRAMs, 504 Recurring costs, design economics, 649–650 Reduced Standard Parasitic Format (RSPF), 643 Reduction operators, HDLs, 703–704 Redundancy, 541–543, 688 Refractory metal, 109 reg type, standard Verilog, 740 Regenerative feedback, small-signal sensing, 512 Regenerators, interconnect engineering, 236 Register files, and multiported SRAMs, 514–515 Register Transfer Level See RTL (Register Transfer Level) abstraction Registers designing from transistors, 19 manufacturing tests verifying, 665 modeling multiported files in HDL, 747–748 scan, 682–683 scannable register design, 684 testing for debugging, 664 Registers, writing with HDLs enabled, 719–720 multiple, 720–721 overview of, 717–718 resettable, 718–719 shift, 724 Regression testing, 671–673 Regularity in hardware and software design, 627 in structured design, 31, 623–625 Reliability metrics, Flash memory, 532 Reliability problems, 246–254 interconnect wearout, 249–251 latchup, 253–254 overview of, 246 overvoltage failure, 252–253 oxide wearout, 247–249 soft errors, 251–252 terminology, 246–247 Repeatability of system, 679 Repeaters, interconnect engineering, 230–232 Replica delay, sense amplifiers, 513 Request (Req) signal, 416–419 Resettable latches and flip-flops, 396–397 Resettable registers, writing with HDLs, 718–719 Resistance influence of scaling on, 256 interconnect modeling and, 214–215 mixed-signal or custom-design flow, 646 pitfall of ignoring in pass transistors, 367 reducing with copper wires, 211 Resistive mode of operation, 63 Resistors, 124–125 Resolution enhancement techniques (RETs), 102–103, 134–135 Resonant currents, 193–194 ReSPF (Reduced Standard Parasitic Format), 643 Restrictive design rules, facilitating RET with, 135 Retention time, Flash memory, 532 Reticle, in photolithography, 101 Retrograde wells, 104–105 RETs (resolution enhancement techniques), 102–103, 134–135 Reverse biased diode, Reverse body bias (RBB), 199–200 RF carrier, software radio design, 618–620 RF (radio frequency) applications, 122, 618–621 RFID (radio-frequency identification) tags, 566 Ring counter, 466 Ripple-carry adder, 436, 491–492 Rise times, 141–142 Robustness, 241–285 historical perspective, 278–283 manufacturing and environmental variability, 241–246 memory design for, 541–544 overview of, 241 pitfalls and fallacies, 277 Index reliability problems See Reliability problems review and exercises, 284–285 scaling See Scaling of static CMOS logic, 327–328 statistical analysis of variability and, 263–274 variation-tolerant design for, 274–277 Rolloff effect, 80 ROM (read-only memory), 527–533 Flash memory, 531–533 modeling in HDL, 748–749 NAND ROMs, 530–531 as nonvolatile memory, 497 overview of, 497, 527–529 programmable ROMs, 529–530 Rotate shifts, 472–476 Routing channels, in physical design, 48–49 Routing, in automated layout, 643–644 Routing track, in stick diagram, 28 Row circuitry, SRAMs dynamic decoders, 508–510 hierarchical wordlines, 508 overview of, 506–507 predecoding, 507–509 sum-addressed decoders, 510 Row decoders, ROM, 528–529 RTL (Register Transfer Level) abstraction defined, 38 design flow, 637–641 overview of, 616 structured design See Structured design strategies Rubylith, 137 SA-F/F (sense-amplifier flip-flop), 399–400 Salicide, 110 Sapphire substrate, SOI, 120 Saturation mode of operation computing delay using transient response, 144–145 in long-channel I-V, 64–68 in MOS transistors, 63 as nonideal I-V effect, 74 Saturation region of operation, 70–71 scale statement, HSPICE, 293–294 Scaled wires, interconnect, 257–258 Scaling, 254–262 historical perspective, 278–282 impact on design, 259–262 interconnect, 257–258 International Technology Roadmap for Semiconductors for, 258 overview of, 254 pitfalls of circuit simulation, 323 pitfalls of failing to plan for, 277 SRAM, 505 transistor, 255–257 Scan design, 403, 682–684 Scanning electron microscopy (SEM), metrology, 113 Schedule, design economics, 651–652 Schichman-Hodges Model, 299 Schockley model, 65, 299 Schottky diode, 20 SCMOS design rules, 117–118 Scribe line, design rules, 116–117 SDFF (Semidynamic Flip-flop), Klass, 399 Sea-of-Gates (SOG) design, 631–632 Searchlines, CAMs, 536 SEC-DED (error-correcting, double errordetecting) codes, 469–470 Second droop, 563 Second-level clock buffers (SLCBs), 572–573 Secondary precharge transistors, dynamic gates, 345–346 Selected signal assignment statements, VHDL, 705 Self-aligned polysilicon gate process, 108–110 Self-aligned process, fabrication, 23–24 Self-bypass path, ALU clock skew example, 391 example using flip-flops, 380–383 example using latches, 385–386 example using time borrowing, 388–389 Self-dual function, addition as, 436 Self-heating controlling reliability problems with, 249– 251 problem of SOI circuits, 363 SEM (scanning electron microscopy), metrology, 113 Semiconductor Industry Association (SIA), 258 Semiconductors historical perspective, 137–138 worldwide market for, 1–2 Semidynamic Flip-flop (SDFF), Klass, 399 Semiglobal wires, interconnect scaling, 257–258 Sense-amplifier flip-flop (SA-F/F), 399–400 Sense amplifiers column circuitry in DRAMs, 525–526 DRAM subarrays and, 523–525 SRAM small-signal sensing and, 512–513 Separations, layout rules as, 113 Sequencing elements comparison of, 423–424 flip-flops See flip-flops latches See latches methodology See Static sequencing element methodology Sequencing overhead defined, 375 of flip-flops, 403 of transparent latches, 404 Sequential circuit design, 375–428 CMOS, 16–19 overview of, 375 Pentium 4/Itanium case study, 423 pitfalls, 422–423 review and exercises, 423–428 sequencing dynamic circuits, 411 sequencing static circuits See Static circuits, sequencing static sequencing elements See Static sequencing element methodology synchronizers See Synchronizers wave pipelining, 420–422 Sequential circuit design, latches and flip-flops, 393–402 conventional CMOS flip-flops, 393–395 conventional CMOS latches, 392–393 differential flip-flops, 399–400 dual edge-triggered flip-flops, 400–401 enabled latches and flip-flops, 397–398 833 incorporating logic into latches, 398–399 Klass Semidynamic Flip-flop (SDFF), 399 overview of, 16–18, 391 pulsed latches, 395–396 radiation-hardened flip-flops, 401–402 resettable latches and flip-flops, 396–397 True Single-phase Clock (TSPC) latches and flip-flops, 402 Sequential circuits, defined, 16 Sequential logic, writing with HDLs, 717–725 counters, 722–723 enabled registers, 719–720 latches, 721–722 multiple registers, 720–721 nonblocking assignments, 733–734 registers, 717–718 resettable registers, 718–719 shift registers, 724 SER (soft error rate) defined, 252 domino noise budget example, 359 radiation-hardened flip-flops decreasing, 401–402 reliability problems, 251–252 robust memory design for improving, 543 Serial access memories defined, 497 queues, 533–535 shift registers, 533 Serial In Parallel Out (SIPO) memory, 533–534 Serial multiplication, 490 Serial/parallel memories, 533–534 Series transistors, 94 SET (single-event transient), 251 Settable latches and flip-flops, 396–397 Setup time, 379–383, 405–408 SEU (single-event upset), 251 Shadow registers, fast binary counters, 465–466 Shallow trench isolation (STI), 106–107, 114 Shared contacted diffusion region, 70 Shielded wires, for crosstalk, 233 Shift registers, 533–534, 724 Shifters alternative shift functions, 476 barrel shifter, 475–476 funnel shifter, 473–475 overview of, 472–473 Shmoo, pitfalls of, 693–695 Shmoo plots, 667, 675–676 Shmooing process, testers, 667 Short channel effect, 74, 80 Short-circuit current, 193 Short Circuit fault model, 677–678 SIA (Semiconductor Industry Association), 258 Sidewall perimeter PS, 72 Sign-magnitude operation, flagged prefix adder, 460–461 Sign select Booth encoder, 484 Signals, SystemVerilog, 707, 709–710 Signals, VHDL code, 700, 707 Signature analysis, testing modules with, 684– 685 Signed multipliers, Booth encoding, 484 SILC (stress-induced leakage current), 248–249 Silicide block mask, circuits, 124 834 Index Silicide layer, 109 Silicidization, 109–110 Silicon compilation, 634–635 creating MOS transistors, 7–8 debug, 659, 673–676 in intrinsic state, 99 making integrated circuits from, 6–7 wafer formation, 100 Silicon dioxide (SiO2) CMOS technology, 105–106 fabrication process, 22 forming gate oxide for transistors, 107–108 inverter cross-section, 20 MOS transistor architecture, Silicon-on-Insulator design See SOI (Siliconon-Insulator) design Silicon on Insulator (SOI), 120, 138 Silicon wafers defined, 19 fabrication process, 21–24 MOS transistor architecture, Simulating mismatches, circuits, 319 Simulation determining effective resistance, 154–155 HDL logic, 701 measuring logical effort, 156 Simulation Program with Integrated Circuit Emphasis See SPICE (Simulation Program with Integrated Circuit Emphasis) Simulators, 287 Single-bit addition, 430–434 Single-ended (large signal) bitline sensing, 511–512 Single-event transient (SET), 251 Single-event upset (SEU), 251 SIPO (Serial In Parallel Out) memory, 533–534 6T SRAM cell, lithographically friendly, 504–505 66 MHz Pentium, 283 Sizing gates under delay constraint, 189 for minimum delay, 171–173 pitfall of oversizing gates, 206 subthreshold circuits, 367 transistors in subthreshold circuits, 365 Sketching, 156 Skew-tolerant latches, 389–391 Skewed gates, 236, 332–333 Skin effect, 219–220 Sklansky (or divide-and-conquer) trees comparing adder architectures, 456–458 higher-valency tree adders, 450–452 overview of, 448–450 parallel-prefix computations, 491–492 sparse tree adders using, 453–454 Slack, delay and, 142 SLCBs (second-level clock buffers), 572–573 Sleep power defined, 195 using input vector control in, 200 using power gating in, 197–198, 519 Slice plans, physical design, 50–51 Slope-based linear model, 173–174 Slopes, 142, 161 Slow inputs, compressors, 486 Slow variables, 244–246 Small-scale integration (SSI), 3–4, 632–634 Small-signal (differential) bitline sensing, 349, 511–513 Smoke test, debugging using, 663–664 SMT (surface mount) packages, 551 Snap-together cells, 49 Sneak paths, MODL, 347–348 SNMs (static noise margins), SRAM cells, 501–503 SOC (System-On-Chip) designs, 29–30 Soft error rate See SER (soft error rate) Software radio applying floorplan for, 626–627 applying hierarchy to, 621–622 applying regularity to, 623–625 structured design example, 617–620 SOG (Sea-of-Gates) design, 631–632 SOI (Silicon on Insulator), 120, 138 SOI (Silicon-on-Insulator) design advantages of, 362 disadvantages of, 362–363 floating body voltage, 361–362 historical perspective, 369 implications for circuit styles, 363–364 overview of, 360–361 processes, 103 summary, 364 Solar cells, 565–566 Source capacitances, 69–70 in detailed MOS gate capacitance model, 70–73 in drain formation, 108–110 in MOS transistors, 8, 62–64 Spacing controlling crosstalk by increasing, 233 interconnect engineering and, 229–230 MOSIS design rules, 118 Spanning-tree adders, 451–452 Sparse tree adders, 451–454, 457 Spectre, 287 Speed Cascode Voltage Switch Logic for, 339 fast binary counters, 465–466 of light set by inductance and capacitance, 218 manufacturing tests verifying, 665 pitfall of disregarding power when designing for, 206 SPEF (Standard Parasitic Exchange Format), 643 SPICE deck common errors, 323–324 defined, 288 sources and passive components, 288–289 transient analysis using, 292–294 transistor DC analysis using, 292 SPICE Explorer, 292 SPICE (Simulation Program with Integrated Circuit Emphasis), 288–298 BSIM models, 300 in circuit design, 44–45 as circuit simulator, 287 common deck errors, 323–324 debugging analog circuits, 675 in diffusion capacitance models, 300–302 HSPICE commands, 298 inverter transient analysis, 292–294 Level models, 299 Level and models, 300 optimization, 296–298 overview of, 288 pitfall of blindly trusting results from, 323 pitfall of replacing thinking with, 323 sources and passive components of, 288–292 subcircuits and measurement, 294–296 transistor DC analysis using, 292 Spines, global clock distribution, 573–574 Split-wordline cells, 514 SPRL (Swing-Restored Pass Transistor Logic), 353–354 Sputtering, 111 Square-law model, 77 SRAM (static RAM), 498–522 area, delay and power of RAMs and register files, 520–522 CAM vs., 535 cells, 499–506 column circuitry, 510–514 large, 515–517 low-power, 517–520 properties, 498–499 register files and multiported, 514–515 row circuitry, 506–510 SSI (small-scale integration), 3–4, 632–634 Stability global clock generators and, 570 SRAM cells and, 501–502 Stack effect, reducing subthreshold leakage, 195–196 Stage effort computing best number of stages, 167–169 defined, 155 sizing for minimum delay, 173 Stages choosing best number of, 166–169 computing Logical Effort of paths, 163–166 Logical Effort notation for number of, 170 Staggered repeaters, for crosstalk, 233–234 Standard cell library, 173 Standard cells building random logic and datapaths from, 48 mapping HDL code into, 41 physical design and, 48–49 Standard datapath latch, 393 Standard deviation normal distributions as, 242 statistical analysis of variability, 263 of threshold voltage, 268–269 Standard Parasitic Exchange Format (SPEF), 643 Standby power, 195 State, in sequential circuits, 375 State retention registers, 198, 408 Statements, HDLs, 702, 703 Static adders, 457 Static circuits, defined, 375 Static circuits, sequencing, 376–391 clock skew, 389–391 max-delay constraints, 379–383 methods, 376–379 min-delay constraints, 383–386 Index overview of, 376 time borrowing, 386–389 Static CMOS, 329–334 asymmetric gates, 332 bubble pushing, 329 compound gates, 329–331 DC transfer characteristics, 88–89 input ordering delay effect, 331 inverters, 332–333 logic, 327–328 logic gates, 9, 363–364 multiple threshold voltages, 334 overview of, 329 P/N ratios, 333–334 Static leakage energy, and variation, 271–272 Static load, ratioed circuits, 334–338 Static noise margins (SNMs), SRAM cells, 501–503 Static power, 194–200 circuit design and, 43 contention current as source of, 197 estimation, 197 gate leakage as source of, 195–196 impact of scaling on design, 261 input vector control, 200 junction leakage as source of, 196–197 multiple threshold voltages and oxide thicknesses, 199 overview of, 194 power gating and, 197–199 subthreshold leakage as source of, 194–195 variable threshold voltages, 199–200 Static RAM See SRAM (static RAM) Static sequencing element methodology, 402–411 characterizing delays, 405–408 choice of elements, 403–405 choosing too late in design cycle, 422–423 design margin and adaptive sequential elements, 409–411 level-converter flip-flops, 408–409 overview of, 402–403 state retention registers, 408 two-phase timing types, 411 Static storage, 375 Static timing analysis, 640, 643–644 Static variations, 267 Statistical analysis of variability, 266–269 Statistical clock skew budgeting, 578–579 STD_LOGIC signals, VHDL, 710 STD_LOGIC type, VHDL, 700–701, 740 STD_LOGIC_VECTOR numbers, VHDL, 709 Step response, power supply, 562–563 Steppers, in photolithography, 101–103 STI (shallow trench isolation), 106–107, 114 Stick diagrams, 28–29 Strained silicon, 121 Strength of signal, 12 Stress-induced leakage current (SILC), 248–249 String select transistor, NAND Flash, 531 Structural domain defined, 615 in design partitioning, 31–32 functional equivalence at various levels of abstraction of, 660–661 levels of design abstraction for, 615–616 structured design for See Structured design strategies Structural HDL, 41 Structural models, 700, 713–716 Structured design strategies, 617–627 hierarchy, 620–622 locality, 626–627 modularity, 625–626 overview of, 30–31 regularity, 623–625 for software and VLSI hardware systems, 627 software radio example, 617–620 understanding, 617–618 Stuck-At fault model, 677–679 Stuck at zero, Stuck-At fault model, 677–679 Subarrays DRAMs, 523–525 large SRAM, 516–517 Subcircuits, and measurement, 294–296 SUBM design rules, 117 Substrate noise, 565 Subsystems, special purpose, 549–614 clocks See Clocks delay-locked loops, 587–590 high-speed links, 597–610 input/output (I/O), 590–597 packaging and cooling See Packaging and cooling phase-locked loops, 580–587 pitfalls and fallacies, 612–613 power distribution See Power distribution subsystem random circuits, 610–612 review and exercises, 613–614 Subthreshold circuit design, 364–367 Subthreshold leakage controlling in low-power SRAMs, 519 as nonideal I-V effect, 80 overview of, 81–83 as pitfall of circuits, 356 solving problem of, 129–130 as source of static power, 194–195 temperature dependence of, 86 Subthreshold memories, low-power SRAMs, 519–520 Subthreshold regime, 364–365 Subthreshold slope, 82, 362 Subtraction, datapaths, 458 Sum-addressed decoders, SRAM row circuitry, 510 Sum-addressed memory, 510 Sum-of-products canonical form, PLAs, 537 Sum (S), 430 See also CPAs (carry-propagate adders) Summary and observations, logical effort of paths, 169–171 Sums of random variables, 264–265 Supply current monitoring (or IDDQ testing), 687 Supply rails, 27 Supply voltage controlling leakage in low-power SRAMs, 518–519 impact of scaling, 261 robustness, 242 SUPREME, 287 Surface mount (SMT) packages, 551 835 Surface potential, 79 Survivability of system, manufacturing tests, 679–680 SWEEP command, 315 Swing-Restored Pass Transistor Logic (SPRL), 353–354 Switching capacitance, 188–190 Switching energy of wire, 222, 256 Switching power, 186, 256 Switching probabilities, and activity factors, 187–188 Symbiotic bypass capacitance, 559 Symbolic layout, 634 Symbols, MOS transistor, 61 Symmetric NORs, 338 Synchronizers, 411–420 arbiters, 419 building faulty, 423 common mistakes, 417–419 communicating between asynchronous clock domains, 416–417 defined, 412 degrees of synchrony, 419–420 metastability, 412–415 overview of, 411–412 simple, 415–416 Synchronous reset, latches and flip-flops, 396–397 Synchronous up/down counter, 464–465 Synchrony, 419–420 Syndrome, signature analyzer, 685 Synthesis, HDL logic, 701 Synthesizable subsets, of HDL, 699 Synthesized design, 49 System-On-Chip (SOC) designs, 29–30 Systematic clock skew sources, 568, 578 Systematic variations, sources of, 266–267 SystemVerilog appendix for See HDLs (Hardware Description Languages) casez statement, 731 how to reference in this book, 699 netlists, 754–755 Verilog vs., 700 T-model wire, 213 Tap sequence, 467 TAP (Test Access Port), 689 Tapeout, 54 Tapped delay lines, 533–534 TAT (trap-assisted tunneling), 84–85 TCAM (ternary CAM), 536 TDDB (time-dependent dielectric breakdown), 248–249 TDM (three-dimensional method), column addition, 487–489 Technology CMOS See CMOS processing technology failing to plan for advances in, 366–367 well-tuned new circuit vs poor example of, 367 Technology node, 258 TEM (Transmission Electron Microscope), 113 temp statement, 302 Temperature controlling interconnect wearout, 249–251 836 Index incorrect operation at low, 695 sequencing element delays and, 407 Temperature dependence interconnect capacitance and, 220 nonideal I-V effects, 85–86 variables effecting robustness, 242–243 Temperature sensors, for packages, 553–555 Temporal locality, in structured design, 626 Ternary CAM (TCAM), 536 Ternary operator (?:), SystemVerilog, 704–705 Test Access Port (TAP), 689 Test fixtures, 666–668, 689–690 Test programs, 667–669 Test structures failing to include process calibration, 136 inserting into scribe line structures, 117 Test vectors defined, 53 fault coverage of, 680 logic verification principles, 670–671 modeling testbenches in HDL, 749–754 Testability See DFT (Design for Testability) Testbenches design verification using, 53 example, overview of, 756 example, writing with SystemVerilog, 757–765 example, writing with VHDL, 766–775 logic verification principles, 671 overview of, 660 writing with HDLs, 749–754 Testers, 666–669 Testing, 659–698 accelerated life, 247 boundary scan, 688–689 building design-for-test into sequencing, 403 debugging, 662–664 design flow, 640–641 Design for Testability See DFT (Design for Testability) design verification via, 53, 55 handlers, 669–670 logic verification via, 660–662, 670–673 manufacturing test principles, 676–681 manufacturing tests, 664–665 overview of, 659–660 pitfalls and fallacies, 690–697 review and exercises, 697–698 silicon debug principles, 673–676 structured design providing, 617 test programs, 668–669 testers and test fixtures, 666–668 in university environment, 689–690 Thermal resistance, 553 Thermal virus, 206 Thermal voltage, 72 Thermoelectric microgenerators, 566 Thermometer code, 579 Third droop, 563 Three-dimensional integrated circuits (3D ICs), 129 Three-dimensional method (TDM), column addition, 487–489 3D ICs (three-dimensional integrated circuits), 129 Threshold drops causing chips to fail, 355 designing circuits with, 494 as nonideal I-V behavior, 87, 92 Threshold implants, 104 Threshold voltage advantage of SOI, 362 beta ratio effects, 90–91 body effect, 79–80 cause of mismatches, 502 comparing in CMOS processes, 313 controlling leakage in low-power SRAMs, 518–519 defined, 79 drain-induced barrier lowering, 80 effect on robustness, 243 extracting with simulations, 306–308 impact of scaling, 261 in negative bias temperature instability, 248 as nonideal I-V effect, 74 short channel effect of, 80 static power and multiple, 119–120, 199, 334 static power and variable, 199–200 statistical analysis of variability and, 268–269 temperature dependence of, 85 Threshold voltage pinning, high-k dialectrics, 120–121 Through-hole pins, of older packages, 550–551 Time borrowing, 386–389, 404–405 Time-dependent dielectric breakdown (TDDB), 248–249 Time-multiplexing, SRAMs, 515 Timescale directive, SystemVerilog, 713 Timing analysis automated layout, 643–644 delay models, 173–174 design flow, 640 Timing analyzer delay models for, 173–174 design flow, 640 overview of, 142 Timing diagram, sequencing element, 378 Timing notation, sequencing element, 377–378 Timing optimization, delay, 142–143 Timing, varying in tester, 667 TinyChips, 117 TLBs (translation lookaside buffers), CAMs, 535 TMR (triple-mode redundancy), 276–277 Tokens, sequential circuit design, 375 Top-level interfaces, logic design, 38 Topography effect, channel lengths, 268 Transient analysis, SPICE, 291 Transient response, delay, 143–145, 148–150 Transistor primitives, SystemVerilog, 754 Transistors choosing inappropriate sizes, 175, 323 CMOS See CMOS (Complementary Metal Oxide Semiconductor) DC analysis using SPICE, 292 design rules, 114–115 forming in Front-End-of-Line phase, 100 historical perspective, 1–6, 278 process enhancements, 119–122 scaling, 255–257 sizing in subthreshold circuits, 365 Translation lookaside buffers (TLBs), CAMs, 535 Transmission Electron Microscope (TEM), 113 Transmission gates creating multiplexer from, 15 DC characteristics, 92–93 defined, 349 implementation of compressor, 487 mixing CMOS with, 351–352 pass transistors and, 12–14 single-bit addition using, 433 Transmission lines, 126 Transmit paths, 619–620, 622 Transparent latches building sequential circuits, 16 choosing for static sequencing element, 404–405 sequencing element delays, 407 Transposed bitlines, 513 Trap-assisted tunneling (TAT), 84–85 Traps, negative bias temperature instability, 248 Tree adders carry-propagate adders and, 447–450 higher-valency, 450–451 sparse, 451–454 Trench capacitors, 523 contact, 135 isolation, 107 overview of, 126–127 Trigate transistors, 130 Triode mode of operation, 63 Triple-mode redundancy (TMR), 276–277 Triple-well processes, 103–105 Tristates, 14–15 True Single-phase Clock (TSPC) latches and flip-flops, 402 TSPC (True Single-phase Clock) latches and flip-flops, 402 Tungsten, processing technology, 110–112 Tunneling current, subthreshold leakage, 83 Twin-well processes, 103, 105 Twisted bitlines, 513, 524 Twisted differential signaling, 233–234 Two's complement array multiplication, 479–480, 492 Type declaration, VHDL signals, 700 Type idiosyncrasies, SystemVerilog and VHDL, 740–742 Typical (nominal) variables, 244–246 UART port, for debugging, 663 UDVS (ultra-dynamic voltage scaling), 192 Ultra-dynamic voltage scaling (UDVS), 192 Unfooted dynamic gates, 340 Uniform distributions, 242 Uniform random variables, 264 Unit transistors, 26 Units, in structured design, 31 University environment, testing in, 689–690 Unsaturated mode of operation, 63 Unsigned array multiplication, 478–479 Up counter (or incrementer), 464–465 Upconversion, 620, 622 Useful operating life, bathtub curve, 247 User Manual, 656 Valency-2 (or radix-2) prefix networks, 438–439, 456–458 Validation, PPL, 587 Index Variability, and scaling, 261 Variability, effects on robustness, 241–246 design corners, 244–246 overview of, 241–242 process variation, 243–244 supply voltage, 242 temperature ranges, 242–243 Variability, statistical analysis of, 263–274 overview of, 263 properties of random variables, 263–266 variation impacts, 269–274 variation sources, 266–269 Variable threshold CMOS (VTCMOS), 199 Variance, statistical analysis, 263–264 Variation impacts, statistical analysis, 269–274 Variation sources, statistical analysis, 266–269 Variation-tolerant design, 274–277 Variation-tolerant (or adaptive) sequential elements, 409–411 VCDL grain, 588 VCDLs (voltage-controlled delay lines), 588–589 VCDs (vector change descriptions), 668–669 VCS logic simulator, 287 VCS (vertical compressor slice), 488 VDD drop, 644 VDD (POWER) CMOS inverter, CMOS NAND gate, as nonideal I-V behavior, 87 positive voltage of MOS transistor, preventing latchup effect, 253–254 strength of signal and, 12 Vector change descriptions (VCDs), 668–669 Velocity saturation creating error in linear delay model, 161–162 defined, 74 as nonideal I-V effect, 75–78 temperature dependence of, 86 Velocity saturation index, 77 Verification See also Testing class chip failures, 696–697 in custom-design flow during manufacturability, 646 design, 53 formal, 640 in general design flow, 637 hierarchy aiding, 620 in logic design, 638–639 personpower costs for, 653 pitfalls of inadequate tools for, 367 pitfalls of insufficient, 657 in platform-based design, 635 regularity aiding, 623 schedule costs for, 652 in structured design, 617 test principles, 670–673 tests, 660–662 virtual components and, 620 Verification Methodology Manual, 680 Verilog appendix for See HDLs (Hardware Description Languages) how to reference in this book, 699 netlists, 43–44 overview of, 41 understanding, 700 Vernier structures, 117 Version control, 672–673 Vertical compressor slice (VCS), 488 Very High Speed Integrated Circuits See VHDL (VHSIC Hardware Description Language) Very large-scale integration (VLSI) circuits, 4, 287 VHDL (VHSIC Hardware Description Language) appendix for See HDLs (Hardware Description Languages) how to reference in this book, 699 overview of, 41 understanding, 700 Via design rules, 116, 118 Victim crosstalk noise effects, 223–224 interconnect simulation, 322 Virtual components, 621, 654–655 VLSI (very large-scale integration) circuits, 4, 287 Volatile memory, 497 Voltage See also Threshold voltage alternative SRAM cells and, 505–506 chip operating at low frequency, 693 dependence causing error in linear delay model, 162 dynamic power and, 190–192 gate leakage depending on gate, 195–196 low-power SRAMs using low, 517–518 overvoltage failures, 252–253 scaling with feature size, 255 selecting gates for subthreshold circuits, 365–366 sequencing element delays and, 407 variables effecting robustness, 242 varying in tester, 667 Voltage-controlled delay lines (VCDLs), 588–589 Voltage domains, 190–191, 208 Voltage regulators, 564–565 VTCOMS (variable threshold CMOS), 199 Wafer bumping, 551 Wafer-to-wafer (W2W) process variations, 243 Wafers formation, 100 photolithography process, 101–103 Wallace trees column addition, 485 defined, 477 implementing compressor, 487 Wasted spins, 692 Watts (W), 182 Wave pipelining, 420–422 Waveforms, pitfalls of circuit simulation, 323 Weak inversion, subthreshold leakage, 81 Wearout, bathtub curve, 247 Well-edge proximity effect, 105 Well-formed modules, 626 Wells defining, 104 837 design rules, 113–114 formation of, 103–105 substrate noise problem in, 565 Wet etching, of metal, 111 Wet oxidation, of silicon, 106 White buffers, adder architecture, 438–440 White space, writing HDLs, 703 Width interconnect engineering and, 229–230 MOSIS design rules, 118 Width/Length (W/L) ratio fallacies of, 94 geometry dependence and, 86 transistor dimensions, 26–27 Wire capacitance applying Logical Effort with wires, 236 computing, 215–217 dynamic power and, 188 gate sizing under delay constraint, 189–190 increasing circuit delay, 220–221 Wire geometry, interconnect, 211–213 Wire pitch, 211 wire type, standard Verilog, 740 Wires See also Interconnect building during metallization process, 110–112 building in Back-End-of-Line phase, 100 Within-die (WID) process variations, 243–244 Within-wafer (WIW) process variations, 243 Word line drivers, 511 Wordlines DRAM See DRAM (Dynamic RAM) dynamic decoders and, 508–509 hierarchical (or divided), 508 ROM, 528 split-wordline cells, 514 Wordslices, logic design, 39–40 Writability constraint, SRAM cells, 501 Write assist, low-power SRAMs, 518 Write drivers, DRAMs, 525–526 Write margin, SRAM cells, 502, 505–506 Write operation, SRAM cells, 500–502 Write ports, multi-ported RAM, 514–515 x (invalid logic level), HDLs, 710 XNOR operation, 471–472 XOR operation carry-ripple adders and, 440–441 carry-skip adders and, 441–443 comparing in multiplier trees, 489 implemented by Boolean unit, 468 linear-feedback shift registers and, 466–467 XOR/XNOR circuit forms, 471–472 Y diagram, design partitioning, 31–32 Yield design for manufacturability, 688 design rules, 113 enhancement guidelines, 135 fundamentals of, 269–270 z (floating value), HDLs, 709–710 Zero insertion force (ZIF) socket, 663 Zero-mean random variables, 264 Zippers, in wordslices, 39 838 Index Credits Figure 1.1 © 1997 Semiconductor Industry Association All Rights Reserved Figure 1.2a Courtesy AT&T Figure 1.2b Courtesy Texas Instruments Figure 1.3a © Copyright 1967 IEEE All Rights Reserved Figure 1.3b Courtesy of Intel Corporation Figure 1.48 Copyright © 2003 The McGraw-Hill Companies, Inc All Rights Reserved Figure 1.71 Courtesy of Intel Corporation Figure 3.1 Courtesy of International Business Machines Corporation Unauthorized use not permitted Figure 3.4 Copyright © 1998 SPIE All Rights Reserved Figure 3.6 © Copyright 2008 IEEE—All Rights Reserved Figure 3.12 Courtesy of International Business Machines Corporation Unauthorized use not permitted Figure 3.13 Courtesy of International Business Machines Corporation Unauthorized use not permitted Figure 3.14 Courtesy of International Business Machines Corporation Unauthorized use not permitted Figure 3.18 © Copyright 2007 IEEE—All Rights Reserved Figure 3.19 (a)(b) © Copyright 2005 IEEE—All Rights Reserved Figure 3.22 Courtesy of International Business Machines Corporation Unauthorized use not permitted Figure 3.30 © Copyright 2005 IEEE—All Rights Reserved Figure 3.31 © Copyright 2006 IEEE—All Rights Reserved Figure 3.32 © Copyright 2008 IBM Corporation All rights reserved Figure 3.34 Courtesy of Intel Corporation Figure 3.35 © Copyright 2003 IEEE—All Rights Reserved Figure 3.38 Courtesy of Intel Corporation Artwork p 136 © 1995–2010 by Michael W Davidson and The Florida State University All Rights Reserved Reproduced with permission Figure 4.25 Copyright © ARM All Rights Reserved Figure 4.41 Copyright © ARM All Rights Reserved Figure 5.11 © Copyright 2004 IEEE—All Rights Reserved Figure 5.19 © Copyright 2007 IEEE—All Rights Reserved Figure 5.21 © Copyright 2007 IEEE—All Rights Reserved Figure 5.26 © Copyright 2005 IEEE—All Rights Reserved Figure 5.27 © Copyright 2002 IEEE—All Rights Reserved Figure 5.28 © Copyright 1997 IEEE—All Rights Reserved Figure 5.30 © Copyright 2009 IEEE—All Rights Reserved Figure 5.33 Courtesy of Intel Corporation Figure 6.2 (a) © Copyright 2010 IEEE—All Rights Reserved Figure 6.2 (b) Figure 6.3 Figure 7.2 Figure 7.3 Figure 7.4 Courtesy of Intel Corporation Courtesy of Intel Corporation © Copyright IBM Corporation All Rights Reserved © Copyright 2001 IEEE—All Rights Reserved From M Pelgrom, “Nanometer CMOS: An Analog Design Challenge!” IEEE Distinguished Lecture, Denver 2006 Reprinted by permission of the author Figure courtesy of Boris Ljevar (NXP) All Rights Reserved Figure 7.7 © Copyright 2010 IEEE—All Rights Reserved Figure 7.8 © Copyright 2010 IEEE—All Rights Reserved Figure 7.11 © Copyright 2010 IEEE—All Rights Reserved Figure 7.15 © Copyright 2010 IEEE—All Rights Reserved Figure 7.16 © 1997 Semiconductor Industry Association All Rights Reserved Figure 7.21 Courtesy Larry Pileggi Figure 7.22 Courtesy of Texas Instruments Figure 7.23 © Copyright 2006 IBM Corporation All rights reserved Figure 7.27 © Copyright 2010 IEEE—All Rights Reserved Figures 7.30–7.38 Courtesy of Intel Corporation Figure 9.62 Courtesy International Business Machines Corporation Unauthorized use not permitted Figure 10.6 © Copyright 2002 IEEE—All Rights Reserved Figure 11.38 © Copyright 2007 IEEE—All Rights Reserved Figure 11.39 © Copyright 2009 IEEE—All Rights Reserved Figure 12.16 (a) © Copyright 2000 IEEE—All Rights Reserved Figure 12.16 (b) © Copyright 2002 IEEE—All Rights Reserved Figure 12.16 (c) © Copyright 2004 IEEE—All Rights Reserved Figure 12.16 (d) © Copyright 2007 IEEE—All Rights Reserved Figure 12.16 (e) © Copyright 2008 IEEE—All Rights Reserved Figure 12.36 © Copyright 2005 IEEE—All Rights Reserved Figure 12.50 © Copyright 2008 IEEE—All Rights Reserved Figure 12.62 © Copyright 2009 IEEE—All Rights Reserved Figure 13.3 Courtesy of Intel Corporation Figure 13.6 © Copyright Sun Microsystems, Inc Figure 13.12 © Copyright 2008 IEEE—All Rights Reserved Figure 13.13 © Copyright 2006 IEEE—All Rights Reserved Figure 14.27 Copyright © 2000–2010 IC Knowledge All Rights Reserved Figure 15.7 © 2009 GGB Industries, reprinted with permision Figure 15.9 © Copyright 2009 IEEE—All Rights Reserved Figure 15.10 Courtesy of Intel Corporation MOSIS SUBM design rules (3 metal, poly with stacked vias & alternate contact rules) Layer N-well Active (diffusion) Poly Select (n or p) Contact (to poly or active) Metal1, Metal2 Via1, Via2 Metal3 Overglass Cut Rule 1.1 1.2 1.3 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.2a 3.3 3.4 3.5 4.1 4.2 4.3 4.4 5.1, 6.1 5.2b, 6.2b 5.3, 6.3 5.4, 6.4 5.5b 5.7b, 6.7b 6.8b 7.1, 9.1 7.2, 9.2 7.3, 8.3, 9.3 7.4, 9.4 8.1, 14.1 8.2, 14.2 15.1 15.2 15.3 15.4 10.1 10.2 10.3 10.4 10.5 Description Width Spacing to well at different potential Spacing to well at same potential Width Spacing to active Source/drain surround by well Substrate/well contact surround by well Spacing to active of opposite type Width Spacing to poly over field oxide Spacing to poly over active Gate extension beyond active Active extension beyond poly Spacing of poly to active Spacing from substrate/well contact to gate Overlap of active Overlap of substrate/well contact Spacing to select Width (exact) Overlap by poly or active Spacing to contact Spacing to gate Spacing of poly contact to other poly Spacing to active/poly for multiple poly/active contacts Spacing of active contact to poly contact Width Spacing to same layer of metal Overlap of contact or via Spacing to metal for lines wider than 10 Q Width (exact) Spacing to via on same layer Width Spacing to metal3 Overlap of via2 Spacing to metal for lines wider than 10 Q Width of bond pad opening Width of probe pad opening Metal3 overlap of overglass cut Spacing of pad metal to unrelated metal Spacing of pad metal to active or poly Rule (Q) 12 18 3 3 3 2 ×2 3 ×2 60 Rm 20 Rm Rm 30 Rm 15 Rm Thank you for purchasing a new copy of CMOS VLSI Design A Circuits and Systems Perspective, Fourth Edition by Neil H.E Weste, David Money Harris The information below provides instruction on how to access the Companion site To access the Companion Website: Go to http://www.pearsonhighered.com/weste/ From here you can register as a First-Time User or Returning User Your student access code will be sent to you by CourseSmart On the registration page, enter your student access code Do not type the dashes You can use lower or uppercase letters Follow the on-screen instructions If you need help during the online registration process, simply click on Need Help? Once your personal Login Name and Password are confirmed, you can begin viewing the Companion Website To login to the website for the first time after you’ve registered: Follow step to return to the Companion Website Then, follow the prompts for "Returning Users" to enter your Login Name and Password Note to Instructors: For access to the Instructor Resource Center, contact your Pearson Representative IMPORTANT: The access code on this page can only be used once to establish a subscription to the Companion Website for CMOS VLSI Design A Circuits and Systems Perspective, Fourth Edition If this access code has already been redeemed, it will no longer be valid If this is the case, you can purchase a subscription by going to the http://www.pearsonhighered.com/weste/ website and selecting "Get Access." ... and still appear in specialized applications 9 .2 Circuit Families 329 9 .2. 1 Static CMOS Designers accustomed to AND and OR functions must learn to think in terms of NAND and NOR to take advantage... using NAND gates has a path logical effort of G = (4/3) × (4/3) = 16/9 and parasitic delay of P = + = The design using the AOI 22 and inverter has a path logical effort of G = (6/3) × = and a parasitic... Inverter AOI21 Y =A A Y Y A Y B C 4 A B C Y Complex AOI Y =A B+C·D A B C A AOI 22 Y =A B+C A B C D Y = A · (B +C) + D · E Y D E A B C Y A B B C D C A A C D E B D E A D 2 C Y B gA = 3/3 gA = 6/3 gA = 6/3