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(BQ) Part 2 book The indispensable PC hardware book has contents Graphics adapters, other interfaces, hard disk drives, floppies and floppy drives, floppies and floppy drives, other peripheral chips and components, multimedia,...and other contents.
18 Our Mathematical Grandmother The MathCo 8087 The four basic arithmetical operations with integers are already integrated on the 8086/88 It is not surprising that the 8086/88 can handle neither floating-point numbers nor transcendental functions; this is carried out by the mathematical coprocessor 8087 It can enhance the performance up to a factor of 100, when compared to software emulations Additionally, the 8087 supports an SOSS/SS CPU in maximum mode with 68 new mnemonics 18.1 8087 Number Formats and Numerical Instruction Set As a mathematical coprocessor, the 8087 can process floating-point numbers directly In the same way as the 80286 and its successors, the 8087 represents all numbers in the temporary real format according to the IEEE standard Figure 6.3 (Chapter 6) shows the number formats that are supported by the 8087 Unfortunately, the 8087 does not implement the IEEE standard for floating-point numbers in a very strict way (not very surprising - the 8087 was available before the standard) The 8087 numeric instruction set is slightly smaller than that for an i387 or 80287XL; for example, the FSETPM (set protected mode) instruction is (of course) missing Further, no functions for evaluating sine and cosine are available But they can be constructed with the help of the tangent A detailed list of all 8087 instructions is given in Appendix Cl 18.2 8087 Pins and Signals Like the 8086/88, the 8087 has 40 pins in all for inputting and outputting signals and supply voltages Usually, the 8087 comes in a 40-pin DIP package Figure 18.1 shows the pin assignment of the 8087 ADlS-ADO (I/O) Pins 39, 2-16 These 16 connections form the 16 data bits when the 8087 is reading or writing data, as well as the lower 16 address bits for addressing memory As is the case with the 8086, these 16 pins form a time-divisionally multiplexed address and data bus A19-A16/S6-S3 (II01 Pins 35-38 These four pins form the four high-order bits of the address bus, as well as four status signals, and form a time-divisionally multiplexed address and control bus During bus cycles controlled by the 8087, the S6, S4 and S3 signals are reserved and held on a high level Additionally, S5 is then always low If the 8086/88 is controlling the bus then the 8087 observes the CPU activity using the signals at pins 56 to S3 471 472 Chapter 16 : AD15 Al+%3 Al 7lS4 A181S5 A19/S6 ms7 RWGTI INT 8087 L J Figure 18.1: 8087 pin assignment The 8087 comes itt a standard DIP pncknge cornprisiq 40 pins BHEIS7 (I/O) Pin This bus high enable signal indicates whether a byte is transferred on the high-order part ADISAD8 of the data bus When the 8086/88 is in control of the bus the 8087 observes the signal at pin 57 supplied by the CPU BUSY (0) Pin 23 If the signal at this pin is high then the 8087 is currently executing a numerical instruction Usually, BUSY is connected to the TEST pin of the 8086/88 The CPU checks the TEST pin and therefore the BUSY signal to determine the completion of a numerical instruction CLK (I) Pin 19 CLK is the clock signal for the 8087 INT (0) Pin 32 The signal output at this pin indicates that during the execution of a numerical instruction 1” the 8087, a non-maskable exception has occurred, for example an overflow The output of tkr signal can be suppressed by interrupt masking in the 8087 Our Mathematical Grandmother The MathCo 8087 473 QSl, QSO (I, I) Pins 24, 25 The signals at these pins indicate the status of the prefetch queue in the 8086/W Thus, the 8087 can observe the CPU’s prefetch queue For (QSl, QSO) the following interpretations hold: (00) the prefetch queue is not active; (01) the first byte of the opcode in the prefetch queue is processed: (10) the prefetch queue is cancelled; (11) a next byte of the opcode in the prefetch queue is processed READY (I) Pin 22 The addressed memory confirms the completion of a data transfer from or to memory with a high-level signal at READY Therefore, like the 8086/88, the 8087 can also insert wait cycles if the memory doesn’t respond quickly enough to an access RESET (I) Pin 21 If this input is high for at least four clock cycles, the 8087 aborts its operation immediately and carries out a processor reset RQ/GTO (I/O) Pin 31 The 8087 uses this pin to get control of the local bus -from the- SOS6/8S so as to execute its own memory cycles RQ/GTO is connected to the CPU’s RQ/GTl pin Normally, the 8086/88 is in control of the bus to read instructions and data If the 8087 accesses the memory because of a LOAD or STORE instruction, it takes over control of the local bus Therefore, both the 8086/88 and the 8087 can act as a local busmaster RQ/GTl (I/O) Pin 33 This pin may be used by another local busmaster to get control of the local bus from the 8087 % zl, so (I/O) Pins 28-26 These three control signals indicate the current bus cycle For the combinations (S2, Sl, SO) the following interpretations hold for bus cycles controlled by the 8087: (OXX) invalid; (1001 invalid; (101) data is read from memory; (110) data is written into 1111) passive state memory; 474 Chapter 18 If the SO86/88 is controlling the bus, the 8087 observes the CPU activity using the signals at pins S2toSO vcc (I) Pin 40 This pin is supplied with the supply voltage of +5 V GND Pins 1, 20 These pins are grounded (usually at V) 18.3 8087 Structure and Functioning The control unit largely comprises a unit for bus control, data buffers, and a prefetch queue The prefetch queue is identical to that in the 8086/88 in a double sense: - It has the same length Immediately after a processor reset the 8087 checks by means of the BHE/S7 signal whether it is connected to an 8086 or 8088 The 8087 adjusts the length of its prefetch queue according to the length in the 8086 (six bytes) or 8088 (four bytes), respectively _ The prefetch queue contains the same instructions By synchronous operation of the 8086/ 88 and 8087, the same bytes (and therefore also the same instructions) are present in the prefetch queues of both CPU and coprocessor Thus, the CU of the coprocessor attends the data bus synchronously to and concurrently with the CPU and fetches instructions to decode Like the other 80x87 coprocessors, the 8087 also has a status, control and tag word, as well as a register stack with eight BO-bit FP-registers Additionally, the two registers for instruction and data pointers are implemented The status word format is shown in Figure 18.2 If bit B is set the numerical unit NU is occupied by a calculation or has issued an interrupt that hasn’t yet been serviced completely If the IX bit is set, a non-maskable exception has occurred and the 8087 has activated its INT output In the PC/XT an NM1 is issued (Beginning with the 80287, IR has been replaced by ES = error status.) The meaning of the remaining bits C3-CO, TOP, PE, LIE, OE, ZE, DE and ZE is the same as for the 80287 The 8087 generates an exception under various circumstances, but some exceptions may be masked Further, you are free to define various modes for rounding, precision and the representation of infinite values For this purpose, the 8087 has a control word, shown in Figure 15.3 Our Mathematical Grandmother - The MathCo 8087 475 Figure 18.3: 8087 control word The IC bit controls the processing of infinite values Projective infinity leads to only one value, namely m If you set IC equal to 0, then the 8087 operates with affine infinity, and two infinite values +a0 and m are possible Beginning with the 80287XL, the IC bit is only present on compatibility grounds because the IEEE standard allows affine infinity only With the M bit, you can mask interrupts globally, in which case the 8087 ignores all exceptions and doesn’t execute an on-chip exception handler This capability has also been removed with the 80287 The function of the remaining bits PM, UM, OM, ZM, DM and IM is the same as in the i387 (Section 6.5) You will find the 8087 tag word in Section 6.5; it is identical to that in the i387 Moreover, the memory images of the instruction and data pointers match those for the 16-bit real format in the i387 They are shown in Figure 6.10 18.4 8087 Memory Cycles An interesting difference between the 8087 and all later 80x87 model occurs in the memory access: the 8087 can access memory on its own; there are no I/O cycles between CPU and coprocessor The 8086/88 distinguishes instructions with memory access from pure arithmetical instructions handed by the 8087 The CPU calculates the operand address according to the addressing scheme indicated, and then the 8086/88 executes a dummy read cycle This cycle differs from a normal read cycle only in that the CPU ignores the data supplied by the memory If the CPU recognizes a coprocessor instruction without a memory operand, it continues with the next struction after the 8087 has signalled via its BUSY pin that it has completed the current struction he 8087 also behaves differently for instructions with and without a memory operand In the rst case, it simply executes an instruction such as FSQRT (square root of a floating-point umber) For an instruction with a memory operand it uses the 8086/88 dummy read cycle in re following way: Fetching an operand from memory: the 8087 reads the address supplied by the CPU in the dummy read cycle via the address bus and stores it in an internal temporary register Then the 8087 reads the data word that is put onto the data bus by the memory If the operand is longer than the data word transferred within this read cycle, the 8087 requests control of the local bus from the 8086/88 Now the 8087 carries out one or more succeeding read cycles on its own The coprocessor uses the memory address fetched during the course of the dummy read cycle and increments it until the whole memory operand is read For example, in the case of the 8088/87 combination, eight memory read cycles are necessary to read a 476 Chapter 18 floating-point number in long real format Afterwards, the 8087 releases control of the loc.ll bus to the 8086/88 again - Writing an operand into memory: in this case the coprocessor also fetches the address output by the CPU in a dummy read cycle, but ignores the memory data appearing on the data bus, Afterwards, the 8087 takes over control of the local bus and writes the operand into memory, starting with the fetched address, in one or more write cycles Because of the dummy read cycle the 8087 doesn’t need its own addressing unit to determine the effective address of the operand with segment, offset and displacement This is advantageous because the 8087, with its 75 000 transistors, integrates far more components on a single chip compared to the 28 000 transistors of the 8086/88, and space is at a premium (remember that the 8087 was born in the 1970s) The 8087 also uses the 8086/88 addressing unit if new instructions have to be fetched into the prefetch queue The CPU addresses the memory to load one or two bytes into the prefetch queue These instruction bytes appear on the data bus The processor status signals keep the 8087 informed about the prefetch processes, and it monitors the bus If the instruction bytes from memory appear on the data bus, the 8087 (and also the 8086/88, of course) loads them into the prefetch queue For the data transfer between memory and coprocessor, no additional I/O bus cycles between CPU and 8087 are necessary Therefore, the LOAD and STORE instructions require more time on an 80287 Don’t be surprised if, for pure mathematical applications, a 10 MHz XT with an 8087 coprocessor is nearly as fast as a 10 MHz AT with an 80287 The 80287 (without XL) runs only at two-thirds of the CPU speed, thus at 6.67MHz Moreover, it requires the additional I/O bus cycles between CPU and 80287 when accessing memory However, the 80286/80287 combination cancels this disadvantage with a more effective bus cycle lasting for only two clock cycles per data transfer at zero wait states, compared to the four clock cycles of the SO86/8O87 combination In the end, both systems give about the same performance 18.5 8086/8087 System Configuration Figure 18.4 shows typical wiring oi the 8087 coprocessor and CPU 8086/88 As they are busmasters, both chips access the same local bus which is connected to memory, the I/O a& dress space and the bus slots via the 8288 bus controller The 8086/88 and the 8087 read and decode the same instruction stream at the same speed, thus they operate s~&zrorrozts/~~ and are supplied with the same clock signal (CLK) by the 8284 clock generator All higher coprocessol-s, however, such as the 80287,387, etc., run asychronously to the CPU For synchronous operntloll of the 8086/88 and 8087, the 8087 must always know the current state of the 8086/88 The 8087 can process its instructions independently of the CPU Even concurrent (parall execution of instructions is possible, but here the problem of resynchronization arises dft’2r completion of the coprocessor instruction After decoding the current ESC instruction, the 8(N~l/ 88 would prefer to execute the next instruction at once, but cannot so because the CPU 11~‘~ to wait for the coprocessor Because of this, the BUSY pin of the 8087 is connected to tllc‘ Our Mathematical Grandmother - The MathCo 8087 477 Figure 18.4: 8086/8087 system configw&m The 8087 hnnnor~izes especinlly well with the 8086/88, and cm therefore be connected to the 8086jSS without difficulties The 8087 uses the same bus controller, the same clock generator, nnd the same interrupt controller as the CPU TEST pin of the 8086/88 When the coprocessor executes an instruction it activates the BUSY signal When it has completed the instruction, it deactivates the signal The WAIT instruction of the 8086/88 causes the CPU to check the TEST pin continuously to observe the BUSY state of the coprocessor Only when the 8087 has deactivated BUSY to signal to the 8086/88 that the current instruction is completed and the 8087 is ready to accept further numeric instructions does the CPU continue with the next instruction Via the QSO and QSl pins, the 8087 detects the status of the 8086/88’s prefetch queue to observe the CPU’s operation Thus, the 8086/88 and 8087 always operate synchronously If an error or an exception occurs during a numerical calculation in the coprocessor, such as overflow or underflow, the 8087 activates its INT output to issue a hardware interrupt request to the CPU Usually, the INT signal of the 8087 is managed by an interrupt controller (the 8259A, for example) and then applied to the 8086/88 But the PC/XT does it in another way: the 8087 hardware interrupt request is supplied to the NM1 input of the 8086/88 The PC/XT has only one 8259A PIC and must therefore save IRQ channels Note that besides the coprocessor interrupt, an error on an extension adapter or a memory parity error may also issue an NM1 corresponding to interrupt Thus, the interrupt handler must be able to locate the source of an NMI Figure 18.4 demonstrates that both the 8086/88 and the 8087 can access the local bus, to read data from memory, for example 8086/88 instructions such as MOV reg, mem or the LOAD instruction of the 8087 carry out a memory access Thus there are two busmasters, each using the local bus independently A simultaneous access of the local bus by the CPU and coprocessor would give rise to a conflict between them, with disastrous consequences Therefore, only one of these two processors may control the local bus, and the transfer- of control between them must be carried out in a strictly defined way Because of this, the RQ/GTl pins of the 8086/88 - - _ and RQ/GlO pins of the 8087 are connected From the description above you_ can see that these _ Pins serve to request and grant local bus control The 8087 uses the RQ/GTO pin to get control 478 Chapter 18 of the local bus for data transfers to and from memory The RQ/GTl pin is available for other busmasters, for example the I/O 8299 coprocessor Therefore, CPU and coprocessor may alternate in controlling the local bus The 8087 bus structure and its bus control signals are equivalent to those of the 8086/88 19 Memory Chips ’ Virtually no other computer element has been the subject of such almost suicidal competition between the world’s leading microelectronic giants over the past ten years as memory chips At the beginning of the PC-era 64 kbit chips and 16 kbit chips were considered to be high-tech But today in our PCs, 16Mbit chips are used, and 256Mbit chips are already running in several laboratories Note that the storage capacity of memory chips is always indicated in bits and not in bytes ,:i Today’s most common Mb memory chip is therefore able to hold four million bits, or 512 kbytes For a main memory of Mbytes, eight of these chips (plus one for parity) are thus required ’ The technological problems of manufacturing such highly-integrated electronic elements are enormous The typical structure size is only about pm, and with the 64 Mbyte chip they will be even less (about 0.3 pm) Human hairs are at least 20 times thicker Moreover, all transistors ‘ and other elements must operate correctly (and at enormous speed); after all, on a 64 Mbyte chip there are more than 200 million (!) transistors, capacitors and resistors If only one of these elements is faulty, then the chip is worthless (but manufacturers have integrated redundant circuits to repair minor malfunctions that will then only affect the overall access time) Thus, it is not surprising that the development of these tiny and quite cheap chips costs several hundred million dollars For the construction of highly integrated memory chips the concept of dynamic RAM (DRAM) is generally accepted today If only the access speed is in question (for example, for fast cache memories), then static RAM (SRAM) is used But both memory types have the disadvantage that they lose their ability to remember as soon as the power supply is switched off or fails They store information in a volatile manner For the boot routines and the PC BIOS, therefore, only a few types of ROM are applicable These memories also hold the stored information after a power-down They store information in a non-volatile manner, but their contents may not be altered, or at least only with some difficulty 19.1 Small and Cheap - DRAM The name dynamic RAM (DRAM) comes from the operation principle of these memory chips They represent the stored information using charges in a capacitor However, all capacitors have the disadvantageous characteristic of losing their charge with the lapse of time, so the chip loses the stored information To avoid this the information must be refreshed periodically or ccdynamically)), that is, the capacitor is recharged according to the information held Figure 19.1 shows the pin assignment of a Mb chip as an example Compared with the processors, we only have to discuss a few pins here A9-Ao (I) Pins 21-24, 27-32 “Th ese t en pins are supplied with the row and column addresses of the accessed memory cells A-7,7 480 Chapter 19 Figure 19.1: Pin ossipment of a 16 Mb chip - - LCAS, UCAS (I) Pins 35, 34 If the corresponding column address strobe pin is on a low level then the DRAM strobes the supplied address and processes it as a column address LCAS is assigned - the low-order data byte 107-100, UCAS the high-order data byte 1015-108 LCAS, UCAS and RAS serve as address control signals for the DRAM chip 1015-100 (I/O) Pins 2-5, 7-10, 41-44, 46-49 These pins are supplied with the write data during a write access, and they provide the read data in the course of a read access RAS (I) Pin 18 If the memory controller applies a low-level signal at this row address strobe pin then the DRAM latches the supplied address and interprets it as a row address WE (1) Pin 17 If the write-enable signal at this pin is on a low level then the DRAM performs a write access GE (I) Pin 33 If the output-enable signal at this pin is on a low level then data is read from the addressed memory cell and output 1293 PCMCIA Socket Services INT lah, Function 86h - SetAdapter This function sets the adapter state c Register Call value Return value AH AL DH DI Carry 86h adapter error code” adapter state2’ IRQ routing for status changes” error if 0 *I bit O=l: power down; bit 0=0: enabled bit l=l: configuration information held; bit l=O: information lost ‘) bit 6~1: IRQ for status change active-high; bit 7~0: IRQ actwe-low for status change enabled; bit 8=0 IRQ disabled bits 0: IRQ level bit 7=1: IRQ ’ INT lah, Function 87h - InquireWindow ; This function provides information about a selected window The calling program must supply t a buffer and store its size (without the first four bytes) in the entry (bufieer_length-4) beginning i at offset OOh The socket service then returns at offset 02h the actual amount of available infori mation If this amount exceeds the buffer size, the information is truncated : i , : ; Register Call value Return value AH AL BH BL 87h adapter wmdow error code” EDI ES Carry buffer offset3’ buffer segment3’ window properties” socket (bit @socket etc.) error if 0 ‘) see M ‘) bit O=l: window can map card memory Into system memory bit l=l: wndow can map common card memory mto system memory bit 2=1’ wlndow can map card I/O ports Into system !iO address area bit 7=1 window uses WAIT for Walt states structure for memory window: content Offset Size word buffer_slze-4 OOh word data sue 02h wlndow table 04h 13 bytes Table for memory window Size content offset bit O=l: wlndow base address programmable, bit 0=0: base address equal FIrstByte 04h word )) Buffer b i t IF bit 1~1: wtndow we programmable, bit l=O we equal MmSize t btt 2=1 wlndow enable/disable wthout reprogramming Appendix M 1294 c Offset Size bit 3=1: wndow can be programmed for 8-bit data bus bit 4=1: window can be programmed for 16.bit data bus bit 5=1: window base address must be an integer multiple of the wndow we bit 6=1: Gindow we must be a power of of ReqGran bit 7=1: card offsets must be specified in units of the window we bit B=l: window can be subdwided into several pages btt 9=!: paging hardware shared by other windows, too bit lC=l: page enable/disable without reprogramming bit l=l' page can be write-protected 06h word (FtrstByte) window base address in system memory (usually a multiple of kbytes) 08h word wlndow end address I” system memory (usually a multiple of kbytes) Oah byte (MEnSize) Obh byte max wmdow we (usually a multiple of kbytes) Och (ReqGran) Odh byte alignment for window base address (as Zentry) Oeh byte alignment for card offset (as Zentw) Ofh byte slowest window access speed (Olh=250 ns, 02h=200 ns 03h=150 ns, 04h=lOO ns) 10h quickest wndow access speed (01 h=250 ns 02h=200 ns 03h=150 ns, 04h=lOO ns) 8uffer byte byte window size (usually a multiple of kbytes) size of the window size unit as Zen@ xtructure for II0 windows: offset Sire Content OOh word buffer-size-4 02h word data size 04h 11 bytes wlndow table Jab/e for I/O window: offset Size content 04h word bit O=l: wmdow base address programmable; bit o=O: base address equal FirstByte bit l=l: window size programmable; bit l=O: size equal MlnSize bit 2=1: window enable/disable without reprogramming bit 3=1: window can be programmed for 8-bit data bus bit 4=1: window can be programmed for 16.bit data bus bit 5=1- wndow base address must be an integer multlple of the window size bit 6=1: window size a power of two of ReqGran bit 7=1: window supports INPACK bit B=l: window supports I/O mapping as EISA btt 9=1 EISA l/O mapping Ignored; bit 9=0: EISA VO mapping enabled (FlrstByte) wndow base address I” system memory (usually a multiple of kbytesi 06h word 08h word window end address in system memory (usually a multiple of kbytes) Oah (MinSre) nxn wlndow we (usually as a multlple of kbytes) Obh byte max wndow size (usually as a multiple of kbytes) Och byte (ReqGran) Odh byte number of address lanes decoded by the window Oeh byte used for EISA l/O address decodlng byte size of the window size unit as Zentv PCMCIA Socket Services 1295 INT lah, Function 88h - GetWindow This function returns the present state of the indicated window Register Call value Return value AH AL BH BL cx DH DL DI Carry aah error code” adapter window socket window 5tate3) wmdow window error if s1ze2) access speed4) base2’ 00 ” see M 2’ II0 wndow: in bytes memory wlndow; I” kbytes I’ btt O=l: card ports are mapped Into system VO address area; bit 0=0: card memory is mapped into system memory bit l=l wndow active, mapping e n a b l e d bit 2=1: l&bit d a t a b u s width; bit 2=0: 8-bft d a t a b u s width bit 3=1: m e m o r y wndow dlvlded Into 16.kbyte pages or IWO window uses EISA I W O m a p p i n g bit e-1: EISA l/O m a p p i n g e n a b l e d ‘) (Olh=250 ns, 02h=200 ns, 03h=150 ns, 04h=lOO ns) INT lah, Function 89h - SetWindow This function sets the state of the window indicated Register Call value Return value AH AL BH BL cx DH DL DI Carry 89h adapter wlndow socket window sizeZi state3’ access speed”) wlndow size” error code” socket error if 0 ‘I see M ‘I i/O wlndow in bytes memory window, I” kbytes 3’ bit O=l’ card ports are mapped Into system l/O address area, bit O&O card memory IS mapped Into system memory bit l=l wndow acttve mapping enabled bit 2=1 16-bit d a t a b u s wdth bft 2=0: 8.bit d a t a b u s wdth bit 3=1 m e m o r y wndow dlvlded Into 16.kbyte bit 4=1: EISA IWO mappIng p a g e s or IWO wndow uses EISA l/O mapptng enabled ” (Olh=ZSO ns 02h=200 ns 03h=150 ns, 04h=lOO ns) 1296 Appendix M INT lah, Function 8ah - GetPage This function determines the present state of the addressed page The returned offset indicates the card offset in Z’complement representation, which must be added to the system address to generate the address within the PCMCIA card , Register Call value Return value AH AL BH BL DL DI Carry 8ah adapter window error code” page page statu?’ 0ffseP error if 0 ‘) see M ‘) bit O=l: card attrlbute memory mapped Into system memory: bit C=O: card common memory mapped into system memory bit l=l: page enabled bit 2=1: page write-protected 3’ in umts of kbytes INT lah, Function 8bh - SetPage This function sets the present state of the addressed page The passed offset indicates the card offset in 2’complement representation, which is added to the system address to generate the address within the PCMCIA card Register Call value Return value AH AL BH BL DL DI Carry 8bh adapter window error code” page page stat& offse? error If 0 ” bit O=l card attribute memory mapped into system memory; bit O=O card common memory mapped Into system WWllO~ bit l=l: page enabled bit 2~1’ page write-protected ” in units of kbvtes PCMCIA Socket Services 1297 l INT lah, Function 8ch - InquireSocket This function provides information about the implemented functions of the addressed socket Register Call value Return value AH AL BH BL DH 8ch adapter error code” PE\DI ES Carry buffer offset4’ buffer segmenP interrupt upon status change” socket callback upon status change” supported indicator? error If 0 I1 see M.3 z sou,ces: bit O=l: write-protection bit l=l: card lock device bit 2=1: card eject bit 3=1’ card insert b i t 4=1 BVDl s i g n a l bit 5=1: BVD2 slgnal b i t 61: RDY/BSY stgnal bit 7=1: CDx signals j’ indicators: b i t O=l: write-protectIon bit l=l: card lock dewce bit 2=1: card eject btt 3=1 c a r d msert bit 4-l: card lock bit 5=1: BVDx signals b i t 61: RDY/BSY slgnal btt 7=1 execute In Place actwe Buffer structure offset Size content OOh word b i t O=l’ memory-only interface 02h dword bltmap of IRQ levels for an actwe-htgh status change Interrupt 06h dword bitmap of IRQ levels for an active-low status change interrupt bit l=l: memory and I/O interface INT lah, Function 8dh - GetSocket This function provides information about the present state of the addressed socket Register Call value Return value AH AL BH BC 8dh adapter error code” interrupt upon status change” socket 1298 Register Appendix M Call value Return value Vcc level Vpp IeveP status change?) indicator state4) interfacefiR@ error if 0 CH CL DH DL DI Carry ” activated mterrupt SOUKCS and occurred status changes: btt 0~1 wte-protection b&t l=l card lock device btt 2=1’ card eject bit 3=1: card wert bit 4=1: BVDl signal bit 5=1 ND2 slgnal bit 6=1: RDY/BSY slgnal blr 7=1: CDx signals 3i high-nibble: Vppl: low-nibble Vpp2 41 states: bit O=l: wte-protectlotbit l=l: card lock dewce bit 2=1: card eject bit 3=1: card Insert bit 4=1: card lock bit 5=1: BVDx signals bit 6=1’ RDYlBSY signal bit 7=1 execute In Place actwe ‘I bit 4: IRQ bit 6=1 IRE4 slgnal inverted (active-high IRQ); bit 6=0: IREQ signal not Inverted bit 7=1: IRQ enabled; bit 7=0: IRQ disabled bit 8=1: memory-only Interface bit 9=1: memory and I/O interface INT lah, Function 8eh - SetSocket This function sets the present state of the addressed socket Register Call value Return value AH AL BH BL CH CL DH DL DI Carry 8eh adapter status change interrupt” socket Vcc level Vpp IeveF) status change?’ Indicator state4) interface/lRQ5’ error code” error if 0 1299 P C M C I A Socket Services I) see M.3 2, activated mterrupt sources and occurred status changes: b i t C=l: write-protectlon bit l=l: card lock device bbt 2=1: card eject bit 3=1: card insert bit 4=1: BVDl s i g n a l bit 5=I: ND2 signal bit 6=1: RDY/BSY s i g n a l b i t 7=1: CDx signals ‘) high-mbble: Vppl; low-nibble Vpp2 41 states b i t C=l: wrote-protection bit l=l: card lock deuce bit 2=1: card eject bit 3=1: card insert bit 4=1: card lock b i t 5=1: BVDx signals bit 6=1: RDY/BSY signal bit 7=1: execute In Place active ‘) b i t 4: IRQ bit 6=1: IREQ s i g n a l Inverted (actwe-high IRQ); bit 6-O IREQ slgnal n o t Inverted bit 7=1: IRQ e n a b l e d ; bit 7=0: IRQ dlsabied bit 8=1: memory-only Interface bit 9=1: memory and IWO interface INT lah, Function 8fh - GetStatus This function returns the present status of various socket units Register Call value Return value AH AL BH BL DH DL DI Carry 8fh adapter error code” card stat& socket socket statu?) indicator state4’ mterface/!RQ” error If -3 ‘) see M.3 *I bit O=l’ write-protection bit l=l: card lock device bit 2=1 c a r d elect bit 3=1 c a r d Insert bit O-1: BVDl s i g n a l b i t 5=1: BVD2 stgnal bit 6=1: RDY/BSY signal b i t 7=1 CDx signals 31 higtl-nibble: V p p l ; low-nibble Vpp2 Appendix M 1302 INT lah, Function 99h - PauseEDC This function pauses an EDC generator Register Call value Retyrn value AH AL BH Carry 99h adapter EDC error code” error if 0 ‘I see M.3 INT lah, Function 9ah - ResumeEDC This function resumes a paused EDC generator Register Call value Return value AH AL BH Carry 9ah adapter EDC error code” error if 0 ‘) see M.3 INT lah, Function 9bh - StopEDC This function stops an EDC generator Register Call value Return value AH AL BH Carry 9bh adapter EDC error code” error if 0 INT lah, Function 9ch - ReadEDC This function reads an EDC generator value Register Call value Return value AH AL BH cx Carry 9ch adapter EDC error code” generator value error if 0 1303 PCMCIA Socket Services INT lah, Function 9dh - GetVendorInfo This function provides information about the vendor The calling program must supply a buffer and store its size (without the first four bytes) in the entry (buffer_size-4) beginning at offset OOh The socket service then returns at offset 02h the amount of actual information available If this amount exceeds the buffer size, the information is truncated Register Call value Return value AH AL BL DX K)DI ES Carry 9dh adapter info type” error code” versior? buffer offset“) buffer segmenfJ’ error If 0 ‘I see M.3 ‘I presently only type defined ” BCD format 4) Buffer structure: offset Size OOh word b u f f e r we - (buf_siz-4) 02h word data we 04h buf_G-4 ASCIIZ string for vendor content INT lah, Function 9eh - AcknowledgeInterrupt This function indicates which socket(s) of an addressed adapter has (have) experienced a status change Register Call value Return value AH AL cx Carry 9eh adapter error code” socke? error If 0 ‘) see M ‘) bit O=socket 0, bit l=socket etc INT lah, Function 9fh - GetSetPriorHandler This function determines (Get) the entry point of the previous handler for INT lah, or sets (Set) this entry point It is thus possible, for example, to set the previous clock interrupt (INT lah, functions OOh-06h) and to remove the socket service from the handler chain Appendix M 1304 Register Call value Return value AH AL BL cx DX Carry 9fh adapter mode @Get, l=Set) handler segment (Setk handler offset (Set) error code” handler segment (Get) handler offset (Get) error if 0 ‘) see M.3 INT lah, Function aOh - Get/Set Socket Service Address (GetSetSSAddr) This function provides information about code and data for the socket service handler or passes data descriptors The calling program must supply a buffer Register Call value Return value AH AL BH BL aOh adapter mode” subfunctior?’ data arrays“’ (Set) buffer offset” (Set) buffer segmenF (Set) error code” :E:DI ES Carry data arrays4’ (Get) buffer offset’) (Get) buffer segment” (Get) error if 0 >) OOh-real mode, Olh=16:16 protected mode, 02h=16:32 protected mode, 03h=00:32 protected mode xl OOh=SS provides Information about code and data in the buffer (Get) Olh=SS provides Information about addltional data in the buffer (Get) OZh=SS accepts an array with pointers to addttlonal data in the buffer (Set) 4, subfunctlon=OOh: number of addItIonal data areas (Get) subfunctlon=Ol h: amount of information about addItIonal data areas (Get) subfunctlork03h: number of pointers to addmonal data areas (Set) ” Buffer structure: Subfunction=OOh content Offset Size OOh dword Itnear 32.bit base address of the code segment 04h dword code segment l!mlt 08h dword offset of entry point Och dword linear 32.bit base address of the data segment 10h dword data segment llmlt 14h dword offset of data area SubfunctforkOlh (one entry for each addItIona/ data segmentiOffset Size content OOh dword linear 32-bit base address of the data segment 04h dword data segment limit 08h dword offset of data area Subfunction=OZh (one entry for each additiona/ Offset Size OOh dword 32.btt offset 04h dword selector 08h dword reserved content data segment) 1305 PCMCIA Socket Services INT lah, Function alh - GetAccessOffsets In a buffer, this function provides the offsets of an adapter-specific access routine to PCMCIA cards which allow an access to the card memory only through a register, that is, I/O ports (the usual method is mapping windows into the system memory) The calling program must supply a buffer Register Call value Return value AH AL BH cx alh adapter mode” number of offset? error code” ;D, ES Carry Offset buffer Segment buffer number of offsets41 error if 0 ” see M *I OOh=real mode, 01 h=16’16 protected mode, 02h=16.32 protected mode, 03h=00:32 protected mode 3) requested number of offsets ‘) avalable number of offsets INT lah, Function aeh - VendorSpecific A call of this function leads in a defined way to a vendor-specific function Vendors are allowed to implement the function in any way With the exception of AH, AL and Carry, the use of all registers is vendor-specific, too Register AH AL Carry Call value Return value aeh adapter error code” error if 0 M.3 Error Codes Code Name Description OOh Olh 02h 03h 04h O6h 07h SUCCESS BAD-ADAPTER BAD-ATTRIBUTE BAD-BASE BAD_EDC BAD_lRQ BAD-OFFSET function completed successfully invalid adapter address Invalid attnbute invalid base address of system memory invalid EDC generator invalid IRQ level Invalid PCMCIA card offset Appendix M 1306 Code Name Description 08h 09h Oah Obh Odh Oeh Ofh llh 12h 14h 15h 16h 17h 18h BAD-PAGE READ-FAILURE BAD-SIZE BAD-SOCKET BAD-TYPE BAD_VCC BAD_VPP BAD-WINDOW WRITE-FAILURE NO-CARD BAD_FUNCTION BAD-MODE BAD-SPEED BUSY invalid page error whrle reading invalid size invalid socket invalid window or interface type invalid Vcc level index invalid Vppl or Vpp2 level Index invalid window error while wrttrng no PCMCIA card in the socket invalid function mode not supported invalid speed socket or PCMCIA card busy M.4 PCMCIA Card Services Summarized - The Card Services provide a system-near interface for PCMCIA slots; calls to the card services are therefore system-dependent For several processes in a system, the card services administer PCMCIA accesses to avoid access conflicts For DOS in real mode (or real mode ROM BIOS), the card services are called through INT lah, function afh ([ah] = afh) M.4.1 Card Services Functions Code Name Description OOh Olh 02h 03h 04h 05h CloseMemory CopyMemory DeregisterClient GetClientlnfo GetConfigurationlnfo GetFirstPartition closes a memory card area copres data of a PCMCIA card removes a clrent from the list of registered clrents provides information about a clrent returns the confrguratron of a socket/PCMCIA card returns informatron about the frrst partitron of the card in a 06h GetFirstRegron 07h 08h 09h Oah Obh GetFirstTuple GetNextPartitron GetNextRegion GetNextTuple GetCardServrceslnfo Och Odh Oeh GetStatus GetTupleData GetFirstClient returns socket returns returns returns returns returns etc.) returns returns returns socket information about the first region of the card In the the first tuple of the specified type information about the next partrtion of the card information about the next region of the card the next tuple of the specrfred type CS Information (number of logrcal sockets, vendor the present status of a PCMCIA card and the socket the content of the last passed tuple the first cirent handle of the registered clrents -.- 1307 PCMCIA Socket Services c Code Name Description Ofh RegisterEraseQueue 10h llh 12h RegisterClrent ResetCard MapLogSocket 13h MapLogWrndow 14h MapMemPage 15h MapPhySocket 16h MapPhyWtndow 17h 18h 19h lah lbh lch ldh leh lfh 2Oh 2lh ModifyWrndow OpenMemory ReadMemory RegisterMTD Release10 ReleaselRQ ReleaseWtndow ReleaseConfrguration Request10 RequestlRQ RequestWindow 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh RequestSocketMask ReturnSSEntry WriteMemory DeregisterEraseQueue CheckEraseQueue ModifyConftguratron RegisterTImer SetRegIon GetNextClient ValidateUS 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h RequestExclustve ReleaseExclusive GetEventMask ReleaseSocketMask RequestConfrguratron SetEventMask AddSocketServrces ReplaceSocketServrces VendorSpecrfrc AdjustResourcelnfo AccessConfrguratronRegrster registers the erase queue of a client being serviced by the card services registers a clrent for service by the card services resets the PCMCIA card In a socket maps a logical socket under card services to the physical adapter and socket values under socket services maps a window handle under card servrces to the physical adapter and window values under socket services maps a memory area of a PCMCIA card to a page in a window maps physrcal adapter and socket values under socket services to a logical socket under card services maps physical adapter and window values under socket services to a window handle under card services modifies the attributes or access speed of a wtndow opens a memory card area reads data from a PCMCIA card via a memory handle registers a memory technology driver MTD releases the previously requested I/O addresses releases previously requested IRQs releases previously requested system memory block resets the socket configuration to memory-only interface requests l/O addresses for a socket requests IRQ for a socket request the mapping of a system memory block to a memory area of a PCMCIA card requests callback upon a socket status change (event) returns the entry pornt Into socket services wrttes data via a memory handle onto a PCMCIA card removes a previously registered erase queue informs about new queue entries modifies a socket and PCMCIA card confrguration registers a trmer for issuing a callback (Events) sets the properties of a PCMCIA card area returns the client handle for the next registered clrent validates the card rnformatron structure (CIS) of a PCMCIA card requests the exclusrve use of a PCMCIA card In a socket releases the exclusive use of a card In a socket returns the bit map mask for Issuing an event releases the previously defined event mask for a socket configures the PCMCIA card rn a socket changes the event mask adds a new 55 handler below the socket servrce level replaces an existrng socket service handler by a new one (vendor-dependent) reads or adjusts the available resources accesses a PCMCIA configuratton regrster 1308 Appendix M M.4.2 Events Events are reported by the socket services to the clients Usually, events are status changes of a socket or the inserted card , Code Event Description 0th 02h 03h 04h 05h 06h 07h BATTERY-DEAD BATTERY-LOW CARD-LOCK CARD-READY CARD-REMOVAL CARD-UNLOCK EJECTION_COMPLETE 08h EJECTION-REQUEST 09h INSERTION_COMPLETE Oah INSERTION_REQUESl Bbh Och Odh Oeh Ofh 10h PM-RESUME PM-SUSPEND EXCLUSIVE_COMPLETE EXCLUSIVE_REQUEST RESET_PHYSlCAL RESET-REQUEST llh 14h 15h 16h 17h CARD-RESET CLIENT-INFO TIMER-EXPIRED SS_UPDATED WRITE-PROTECT 40h 80h 81h 82h CARD_INSERTION RESET-COMPLETE ERASE-COMPLETE REGISTRATlON_COMPLETE battery dead, data lost battery low, data still o.k mechanical - lock has locked the inserted card RDY/BSY signal has changed from busy to ready card has been removed from a PCMCIA socket mechanical lock has released the inserted card card has been ejected from the socket by an automatic ejection device card should be ejected from the socket by an automatrc ejection device card has been inserted into the socket by an automatic insertion device card should be inserted into the socket by an automatic insertion device power management should power-up socket and card power management should power-down socket and card client has been granted an exclusrve access to a PCMCIA card client attempts to gc$ an exclusive access to a PCMCIA card hardware reset for a PCMCIA card in a socket client has requested a hardware reset for a PCMCIA card in a socket hardware reset for the card in a socket completed client should return information timer expired socket support via socket services has been changed write-protect status for the PCMCIA card which IS Inserted rn the socket has changed a PCMCIA card has been inserted reset rn the background complete erase in the background complete registration in the background complete 1309 PCMCIA Socket Services M.4.3 Error Codes Code Name Description OOh Olh 02h 03h 04h 05h 06h 07h 08h 09h Oah Obh Och Odh Oeh Ofh 10h llh 12h 13h ,14h ,15h J6h ;17h 18h :19h lah ‘1 bh +ch ‘ldh lleh lfh ,2Oh 2lh SUCCESS BAD-ADAPTER BAD_ATTRIBUTE BAD-BASE BAD_EDC - function completed successfully adapter invalid attribute invalid system memory base invalid EDC generator Invalid reserved IRQ level invalid PCMCIA card offset invalid page invalld error while reading invalid size invalld socket reserved window or interface type invalid Vcc level Index invalid Vppl or Vpp2 level index invalid reserved wlndow invalid error while writing reserved no PCMCIA card in socket function not supported mode not supported speed invalid socket or PCMCIA card busy undefined error occurred medium write-protected function argument length invalid one or more function arguments invalid configuration already locked resource already in use no more of the requested items no more resources handle invalid BAD_IRQ BAD-OFFSET BAD-PAGE READ-FAILURE BAD-SIZE BAD-SOCKET BAD_lYPE BAD_VCC BAD_VPP BAD-WINDOW WRITE-FAILURE NO-CARD UNSUPPORTED_FUNCTION UNSUPPORTED_MODE BAD-SPEED BUSY GENERAL-FAILURE WRITE-PROTECTED BAD_ARG_LENGTH BAD_ARGS CONFIGURATION_LOCKED IN-USE NO_MORE_ITEMS OUT_OF_RESOURCE BAD-HANDLE ... controller (the 825 9A, for example) and then applied to the 8086/88 But the PC/ XT does it in another way: the 8087 hardware interrupt request is supplied to the NM1 input of the 8086/88 The PC/ XT has... and the drain is part of the bit line if the word line W is selected by the row decoder, then the electric field below the gate that is part of the word line lowers the resistance value of the. .. another local busmaster to get control of the local bus from the 8087 % zl, so (I/O) Pins 28 -26 These three control signals indicate the current bus cycle For the combinations (S2, Sl, SO) the