Design Methodology with System Generator in Simulink of a FHSS Transceiver on FPGA 307 SPLITTING FILTERS FHSS_FILTERED 2 SYNCHRONIZATION _FILTERED 1 Terminator 4 Terminator 3 Term inat or 2 Term inat or 1 FIR Compiler 4.0 _SYNCHRONIZATION din dout rfd rdy FIR Compiler 4.0_FFHSS din dout rfd rdy Coefficients _HPF FDATool Coefficients _ BPF FDATool SF_IN 1 Fix_20_17Fix_18_14 Bool Bool Bool Bool Fi x _ 7 _ 5 Fig. 23. Splitting filters block diagram 1.95 2 2.05 2.1 2.15 2.2 2.25 2.3 x 10 -5 -2 -1 0 1 2 1.95 2 2.05 2.1 2.15 2.2 2.25 2.3 x 10 -5 -1 -0.5 0 0.5 1 1.95 2 2.05 2.1 2.15 2.2 2.25 2.3 x 10 -5 -1 -0.5 0 0.5 1 Fig. 24. Splitting filters signals: a) input, b) FHSS filtered, c) synchronization filtered Fig. 25. Filter Design and Analysis Tool dialog window a) b) c) Applications of MATLAB in Science and Engineering 308 6.2 Synchronization recovery The input of this system is the synchronization filtered, in its output gets the most significant four bits of the pseudorandom code (Fig. 26). It is formed (Fig. 27) by a 9 MHz recover, a synchronous demodulator, a load and enable generators, and a Linear Feedback Shift Register code generator. 0 0.5 1 1.5 2 2.5 3 3. 5 4 4.5 5 x 10 -5 -1 -0.5 0 0.5 1 0 0.5 1 1.5 2 2.5 3 3. 5 4 4.5 5 x 10 -5 0 2 4 6 8 10 12 14 16 1.6 1.7 1.8 1.9 2 2.1 2. 2 2.3 2.4 2.5 x 10 -5 -1 -0.5 0 0.5 1 1.6 1.7 1.8 1.9 2 2.1 2. 2 2.3 2.4 2.5 x 10 -5 0 2 4 6 8 10 12 14 16 Fig. 26. Synchronization recovery signals: a) synchronization filtered, b) code recovered SYNCHRONIZATION RECOV ERY CODE _RECOVERED 1 SYNCHRONOUS DEMODULA TOR SR_IN 9_MH z LENGTH _DEMODULATED LOAD GENERATOR LENGTH_DEMODULATED LOAD LFS R CODE GENERATOR LOAD ENABLE CODE_RECOVERED ENABLE GENERATOR 9_MHz ENABLE (1.5 MHz) 9 MHz RECOV ER SR_IN 9_MHz SR_IN 1 Fix_20_17 Bool Bool Bool UFix_4_0UFix_1_0 Fig. 27. Synchronization recovery block diagram 6.2.1 Carrier recover (9 MHz) This system recovers the carrier of the synchronization signal (Fig. 28). Initially the phase- modulated signal is squared and filtered to get double the carrier frequency with an 18 MHz band pass filter (Fig. 29); the sample frequency is 180 MHz. The 18 MHz signal is squared by a comparator and a pulse is generated with each rising edge. Finally, an accumulator generates a 9 MHz squared signal with 50% duty cycle. 9 MHz RECOVER 9_MHz 1 Terminator 1 Terminator Relational a b a>b z -0 Reinterpret reinterpret Mult a b (ab ) z -0 FIR Compiler 4.0_18 MHz din dout rfd rdy FDATool _BPF FDATool Express ion a b a & ~b Delay z -1 Constant 0 Accumulator b q SR_IN 1 Fix_20_17 Fix_26_24 Bool Bool Fix_40_37 Bool UFix_1_0 Bool Bool UFix_1_0UFix_1_0 Fig. 28. Carrier recovery of 9 MHz block diagram 6.2.2 Synchronous demodulator The block in Fig. 30 is a phase demodulator of the synchronization signal. The output indicates the length of the code with two consecutive edges of the signal (Fig. 31). The a) b) Design Methodology with System Generator in Simulink of a FHSS Transceiver on FPGA 309 unipolar square 9 MHz carrier is converted to bipolar; in this way, the multiplier output assumes non-zero values in each semicycle. The delay block for the carrier ensures the synchronous demodulation. The output of the low pass filter is introduced to a comparator to get the length signal demodulated. 2.02 2.04 2.06 2.08 2.1 2.12 2.14 2.16 2.18 2.2 x 10 -5 -1 0 1 2.02 2.04 2.06 2.08 2.1 2.12 2.14 2.16 2.18 2.2 x 10 -5 0 0.5 1 2.02 2.04 2.06 2.08 2.1 2.12 2.14 2.16 2.18 2.2 x 10 -5 -0.4 -0.2 0 0.2 2.02 2.04 2.06 2.08 2.1 2.12 2.14 2.16 2.18 2.2 x 10 -5 0 0.5 1 2.02 2.04 2.06 2.08 2.1 2.12 2.14 2.16 2.18 2.2 x 10 -5 0 0.5 1 2.02 2.04 2.06 2.08 2.1 2.12 2.14 2.16 2.18 2.2 x 10 -5 0 0.5 1 Fig. 29. Carrier recovery signals: a) synchronization filtered input, b) squared signal, c) 18 MHz filtered, d) 18 MHz square wave, e) pulse with rising edge, f) 9 MHz square wave SYNCHRONOUS DEMODULATO R LENGTH _DEMODULATED 1 Terminator 51 Terminator Relational 1 a b a>b z -0 Mult 1 a b (ab ) z -0 FIR Compiler 4.0_LOW_PASS_FILTER din dout rfd rdy FDATool _LPF FDATool Delay z -4 Constant 2 0 Constant 1 -1 CMult x 2 AddSub a b a + b 9_MHz 2 SR_IN 1 Fix_22_17 Bool Bool Fix_36_31 UFix_1_0 Fix _20_17 Bool Fix _2_0 UFix_3_0 Fix_2_0 UFix_1_0 Fix _2_0 Fig. 30. Synchronous demodulator block diagram 2.5 3 3.5 4 4.5 x 10 -5 -1 -0.5 0 0.5 1 2.5 3 3.5 4 4.5 x 10 -5 -1 -0.5 0 0.5 1 2.5 3 3.5 4 4.5 x 10 -5 -1 -0.5 0 0.5 1 2.5 3 3.5 4 4.5 x 10 -5 -0.5 0 0.5 2.5 3 3.5 4 4.5 x 10 -5 0 0.5 1 2.05 2.1 2. 15 2.2 2.25 x 10 -5 -1 -0.5 0 0.5 1 2.05 2.1 2. 15 2.2 2.25 x 10 -5 -1 -0.5 0 0.5 1 2.05 2.1 2. 15 2.2 2.25 x 10 -5 -1 -0.5 0 0.5 1 2.05 2.1 2. 15 2.2 2.25 x 10 -5 -0.5 0 0.5 2.05 2.1 2. 15 2.2 2.25 x 10 -5 0 0.5 1 Fig. 31. Synchronous demodulator signals: a) synchronization input, b) 9 MHz multiplier input, c) multiplier output, d) filter output, e) length demodulated a) b) c) d) e) a) b) c) d) e) f) Applications of MATLAB in Science and Engineering 310 6.2.3 Load generator The circuit in Fig. 32 produces a pulse with the rising or falling edge at the input (Fig. 33). The output signal loads the initial value “11111” in the Linear Feedback Shift Register of the code generator in the receiver. LOAD GENERATO R LOAD 1 Expression a b (a & ~b) | (~a & b) Delay z -1 LENGTH _ DEMODULATED 1 Bool Bool Bool Fig. 32. Load generator 2.14 2.145 2.15 2.155 x 10 -5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 2.14 2.145 2.15 2.155 x 10 -5 -0.2 0 0.2 0.4 0.6 0.8 1 2.14 2.145 2.15 2.155 x 10 -5 -0.2 0 0.2 0.4 0.6 0.8 1 4.208 4.21 4.212 4.214 4.216 4.218 4.22 4. 222 x 10 -5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 4.208 4.21 4.212 4.214 4.216 4.218 4.22 4. 222 x 10 -5 -0.2 0 0.2 0.4 0.6 0.8 1 4.208 4.21 4.212 4.214 4.216 4.218 4.22 4. 222 x 10 -5 -0.2 0 0.2 0.4 0.6 0.8 1 Fig. 33. Load generator signals: a) input, b) delayed input, c) output 6.2.4 Enable generator The input of this system (Fig. 34) is the 9 MHz square carrier and generates a 1.5 MHz enable signal. A pulse is obtained with the rising edge at the input (Fig. 35). This signal is used as enable signal in a six states counter; a comparator checks when the counter output is zero. Finally, a pulse is generated with each rising edge of the comparator output. The output signal has the chip frequency, it will be used as input in a Linear Feedback Shift Register to recover the pseudorandom code. ENABLE GENERATO R ENABLE (1.5 MHz) 1 Relational 2 a b a=b z -0 Ex pression 1 a b a & ~b Expression a b a & ~b Delay 1 z -1 Delay z -1 Counter en out Convert 2 cast Constant 3 0 9_MHz 1 UFix _1_0 UFix_1_0 UFix_3_0 UFix_1_0 Bool Bool UFix_1_0 Bool Bool Fig. 34. Enable generator block diagram a) b) c) Design Methodology with System Generator in Simulink of a FHSS Transceiver on FPGA 311 1.02 1.04 1. 06 1.08 1.1 1.12 1.14 1. 16 1.18 1.2 x 10 -5 0 0.5 1 1.02 1.04 1. 06 1.08 1.1 1.12 1.14 1. 16 1.18 1.2 x 10 -5 0 0.5 1 1.02 1.04 1. 06 1.08 1.1 1.12 1.14 1. 16 1.18 1.2 x 10 -5 0 2 4 6 1.02 1.04 1. 06 1.08 1.1 1.12 1.14 1. 16 1.18 1.2 x 10 -5 0 0.5 1 1.02 1.04 1. 06 1.08 1.1 1.12 1.14 1. 16 1.18 1.2 x 10 -5 0 0.5 1 Fig. 35. Enable generator signals: a) 9 MHz input, b) internal pulse with the input rising edge, c) counter output, d) zero value in the counter output, e) enable generator output 6.2.5 Linear feedback shift register code generator This system is a LFSR similar to the code generator in the transmitter (Fig. 36); with the exceptions of the load signal to initialize the “11111” value and the enable signal to generate the 1.5 MHz output rate. A delay block synchronizes the load and enable signal. The LFSR inputs and the value of the code recovered are shown in Fig. 37. LFSR CODE GENERATO R CODE _RECOVERED 1 Slice [a:b] LFSR din load en dout Delay z -5 Constant 31 ENABLE 2 LOAD 1 UFix _5_0 UFix _5_0 UFix _4_0Bool Bool Bool Fig. 36. Linear Feedback Shift Register code generator block diagram 0 1 2 3 4 5 6 7 x 10 -5 0 0.5 1 0 1 2 3 4 5 6 7 x 10 -5 0 0.5 1 0 1 2 3 4 5 6 7 x 10 -5 0 5 10 15 Fig. 37. Linear Feedback Shift Register code generator signals: a) LFSR load input, b) LFSR enable input, c) code recovered a) b) c) a) b) c) d) e) Applications of MATLAB in Science and Engineering 312 6.3 Local oscillators The code recovered is the local oscillators input (Fig. 38). The two oscillators were designed using two Direct Digital Synthesizer blocks, and the four bits input code must be converted to the input format of the DDS block. The frequency of the oscillator F_0 output (Fig. 39) is the transmitted frequency if the data in the transmitter is “0” minus 10.7 MHz; in other words, the left side of Table 1 minus 10.7 MHz. Consequently the value of the intermediate frequency in the receiver is 10.7 MHz. Similarly, the frequency of the oscillator F_1 output is the transmitted frequency if the data in the transmitter is “1” minus 10.7 MHz; in the same way, the right side of Table 1 minus 10.7 MHz. LOCAL OSCILLATORS F_0 2 F_1 1 OSCILLATOR _F_1 In 2 F_1 OSCILLATOR _F_0 In 2 F_0 CODE _IN 1 UFix _4_0 Fix _6_5 Fix _6_5 Fig. 38. Local oscillators block diagram OSCILLATO R _ F _ 0 F_0 1 DDS Compiler 2.1 we data sine Constant 2 1 Constant 1 0.076019287109375 CMult x 0.00853 AddSub a b a + b In 2 1 UFix _4_0 Fix_29_29 UFix _16_16 UFix_20_16 Bool Fix _6_5 Fig. 39. Oscillator F_0 block diagram 2.7 2.75 2.8 2.85 2.9 2.95 x 10 -5 0 5 10 15 2.7 2.75 2.8 2.85 2.9 2.95 x 10 -5 -1 -0.5 0 0.5 1 2.7 2.75 2.8 2.85 2.9 2.95 x 10 -5 -1 -0.5 0 0.5 1 Fig. 40. Local oscillators signals: a) local oscillators input, b) oscillator F_0 output, c) oscillator F_1 output a) b) c) Design Methodology with System Generator in Simulink of a FHSS Transceiver on FPGA 313 6.4 Double branch demodulator This demodulator is formed by two similar envelope detectors (Fig. 41). The inputs are the FHSS filtered signal and the local oscillators outputs. The FHSS filtered signal is delayed to keep the synchronization with the local oscillators frequencies. The top branch gets the waveform of the data and the bottom branch the inverter data. Lastly, the two outputs are compared and final output is the binary demodulated data. DOUBLE BRANCH DEMODULATO R DEMODULATED _DATA 1 Relational a b a>b z -0 DATA_ N_DEMODULATOR F_0 FHSS_IN DATA_N DATA_ DEMODULATOR F_1 FHSS_IN DATA F_0 3 FHSS_IN 2 F_1 1 Bool Fix _6_5 Fix _6_5 Fix_18_14 Fix_41_38 Fix_41_38 Fig. 41. Double branch demodulator block diagram The Fig. 42 is the top branch block diagram. The mixer of the branch is the first multiplier and the intermediate frequency band pass filter. The second multiplier and the low pass filter is the envelope detector. The Fig. 43 shows the signals in the demodulator. DATA _ DEMODULATOR DATA 1 Terminator 4 Terminator 3 Terminator 2 Terminator 1 Mult 1 a b (ab ) z -0 Mult a b (ab ) z -0 FIR Compiler 4.0_LOW_PASS_FILTER din dout rfd rdy FIR Compiler 4.0_IF_10 .7 MHz din dout rfd rdy FDATool _LPF FDATool FDATool _IF FDATool FHSS_IN 2 F_1 1 Fix_24_19 Bool Bool Fix_37_31 Bool Bool Fix_26_24 Fix _41_38Fix_6_5 Fix_18_14 Fig. 42. Top branch demodulator block diagram 7. Channel simulation Once the design of the transceiver has been finished, the performances can be tested inserting a channel between the transmitter and the receiver. For this purpose, an Additive White Gaussian Noise (AWGN) Simulink channel was chosen (Fig. 44). In this channel, the signal-to-noise power ratio is fixed by the designer. The Bit Error Rate (BER) was measured with the Error Rate Calculation block, where the delay between the data must be specified. Besides, the instant of synchronization in the receiver (20 microseconds) is indicated to start the bit error counter. This block generates three values: the first is the Bit Error Rate, the second is the number of errors, and the third is the number of bits tested. Finally, the BER is represented versus the signal-to-noise power ratio (Fig. 45). Applications of MATLAB in Science and Engineering 314 4 4.2 4.4 4.6 4.8 5 x 10 -5 -0.5 0 0.5 4 4.2 4.4 4. 6 4.8 5 x 10 -5 0 0.2 4 4.2 4.4 4. 6 4.8 5 x 10 -5 0 0.05 0.1 4 4.2 4.4 4. 6 4.8 5 x 10 -5 -0.5 0 0.5 4 4.2 4.4 4. 6 4.8 5 x 10 -5 0 0.2 4 4.2 4.4 4. 6 4.8 5 x 10 -5 0 0.05 0.1 4 4.2 4.4 4. 6 4.8 5 x 10 -5 0 0.5 1 Fig. 43. Double branch demodulator signals: a) intermediate frequency filter output in the top branch, b) squared signal in the top branch, c) low pass filter output in the top branch, d) intermediate frequency filter output in the bottom branch, e) squared signal in the bottom branch, f) low pass filter output in the bottom branch, g) demodulated output Terminator Scope FHSS TRANSMITTER EXTERNAL_DATA DATA_CONTROL FHSS_SYNCHRONIZATION FB DATA FHSS RECEIVER RX_IN DE MOD UL ATED _ DATA Error Rate Calculation Error Rate Calculation Tx Rx Display 0 0 121 Constant 1 0 Constant 0 AWGN Channel AWGN System Generator Bool double double double double double double double Fig. 44. Error rate calculation in presence of Additive White Gaussian Noise 0 2 4 6 8 10 12 14 16 18 20 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Fig. 45. Bit Error Rate represented versus the signal-to-noise power ratio (decibels) Signal to noise relation ( dB ) Bit Error Rate a) b) c) d) e) f) g) Design Methodology with System Generator in Simulink of a FHSS Transceiver on FPGA 315 8. Simulation and compilation with ISE After the system has been simulated with Simulink, it can be compiled with System Generator. The chosen device is a Virtex 4 FPGA, and the hardware description language is Verilog. A project is then generated for Integrated System Environment, which includes the files for the structural description of the system. The syntax of the Verilog files can be checked, and the synthesis and behavioral simulation of the system can be executed (Fig. 46). Thereafter, the implementation of the design allows the timing simulation of the transceiver (Fig. 47). Lastly, the programming file is generated for the chosen FPGA. Fig. 46. A long behavioral simulation of the FHSS transceiver using ISE (40 microseconds) Fig. 47. Timing simulation of the FHSS transceiver using ISE (80 nanoseconds) The Integrated System Environment software provides a power estimator that indicates a dissipation of 0.52 watts in the FPGA, and an estimated temperature of 31.4 degrees centigrade. The FPGA core is supplied with 1.2 volts and the input-output pins support the Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) volts standard. The design uses 491 of the 521 FPGA multipliers. The occupation rate of input-output pins in the FPGA is about 12.3%. However, this occupation rate can be reduced until 3.3% if internal signals are not checked. 9. Conclusions and future work With this design methodology the typical advantageous features of using programmable digital devices are reached. Repeating a design consists in reprogramming the FPGA in the chosen board. The design and simulation times are decreased, consequently the time to Applications of MATLAB in Science and Engineering 316 market is minimizing. The used tool permits great flexibility; in others words, the design parameters can be changed and new features can be checked within several minutes. The flexibility allows to change the Direct Digital Synthesizers and filters parameters and to check its performances. The Simulink simulations are easy to run, and the signals are shown in floating point format which make easier its analysis. These simulations are possible even before the compilation of the System Generator blocks to obtain the hardware description language files. With the System Generator it is possible to simulate the full transceiver, the transmitter and the receiver can be connected through a channel. Moreover, it is possible to simulate the transmission in presence of interference, distortion, multipath and other spread spectrum signals using different codes. 10. References Analog Devices (2011). AD9851 DDS. URL: www.analog.com/static/imported- files/data_sheets/AD9851.pdf, active on April 2011 Hauck, S. & DeHon, A. (2008). Reconfigurable Computing, Elsevier, ISBN 978-0-12-370522-8, USA MathWorks. (2011). Simulink. URL: www.mathworks.com/products/simulink, active on April 2011 Maxfield, C. (2004). The Design Warrior's Guide to FPGAs, Elseiver, ISBN 0750676043, New York, USA Palnitkar, S. (2003).Verilog HDL. Prentice Hall, ISBN 9780130449115, USA Pedroni, V. (2004). Circuit Design with VHDL, The MIT Press, ISBN 0-262-16224-5, USA Pérez, S.; Rabadán, J.; Delgado, F.; Velázquez, J & Pérez, R. (2003). Design of a synchronous Fast Frequency Hopping Spread Spectrum transceiver for indoor Wireless Optical Communications based on Programmable Logic Devices and Direct Digital Synthesizers, Proceedings of XVIII Conference on Design of Circuits and Integrated Systems, pp. 737-742, ISBN 84-87087-40-X, Ciudad Real, Spain, November, 2003. Simon, M.; Omura, J.; Scholtz, R. & Levitt, B. (1994). Spread Spectrum Communications Handbook, McGraw-Hill Professional, ISBN 0071382151, USA Xilinx (2011). System Generator. URL: www.xilinx.com/tools/sysgen.htm, active on April 2011 [...]... features of Simulink focusing on modeling and control of mechanical systems In the first part, we present the method for creating new Simulink models using different toolboxes to customize their appearance and use Then in the second 318 Applications of MATLAB in Science and Engineering part, we discuss Simulink and MATLAB features useful for viewing and analyzing simulation results In the third part, ... types of modeling of mechanical systems used in Simulink Finally, we give two examples of modeling and control, illustrating the methods presented in the previous parts The first example describes the Stewart platform and the second one describes a three Degree of Freedom (3-Dof) stabilized platform 2 Getting started with Simulink Simulink is a software package for modeling, simulating, and analyzing... Systems in Simulink of Matlab 323 3 Viewing and analyzing simulation results Output trajectories from Simulink can be plotted using one of three methods (The MathWorks, 1999):  Feeding a signal into either a Scope or an XY Graph block  Writing output to return variables and using MATLAB plotting commands  Writing output to the workspace using To Workspace blocks and plotting the results using MATLAB. .. http://www1.mengr.tamu.edu/aparlos/MEEN651/SimulinkTutorial.pdf 334 Applications of MATLAB in Science and Engineering Popinchalk, S (2009) Modeling Mechanical Systems: The Double Pendulum, In: Mathworks Blogs Seth on Simulink, February 26th 2009, Available from: http://blogs.mathworks.com/seth/2009/02/26/modeling-mechanical-systemsthe-double-pendulum/ Stewart, D (1965) A platform with six degrees of freedom, Proceedings of the Institution of. .. plate at six points by universal joints as shown in fig 15 Each leg has two parts, an upper and a lower, connected by a cylindrical joint Each upper leg is connected to the top plate by another universal joint Thus the platform has 6*2 + 1 = 13 mobile parts and 6*3 = 18 joints connecting the parts Fig 15 Stewart platform 330 Applications of MATLAB in Science and Engineering 5.2.1 Modeling the physical... Each of the legs is a subsystem containing the individual Body and Joint blocks that make up the whole leg (see fig 17) Modeling and Control of Mechanical Systems in Simulink of Matlab 331 Fig 17 Leg Subsystem content To visualise the content of this subsystem, select one of the leg subsystems and right-click select Look Under Mask Fig 18 Stewart Platform Control Design Model 332 Applications of MATLAB. ..15 Modeling and Control of Mechanical Systems in Simulink of Matlab Leghmizi Said and Boumediene Latifa College of Automation, Harbin Engineering University China 1 Introduction Mechanical systems are types of physical systems This is why it is important to study and control them using information about their structure to describe their particular nature Dynamics of Multi-Body Systems (MBS)... use of state observers The integral reconstruction of the state variables is carried out by means of elementary algebraic manipulations of the system model along with suitable 336 Applications of MATLAB in Science and Engineering invocation of the system model observability property The purpose of integral reconstructors is to get expressions for the unmeasured states in terms of inputs, outputs, and. .. equations of motion of multi-body systems in novel forms Furthermore, to prove the efficiency of these models and simulate them, efficient software for modeling is needed In the last few years, Simulink has become the most widely used software package in academia and industry for modeling and simulating mechanical systems Used heavily in industry, it is credited with reducing the development of most... Modeling using SimMechanics SimMechanics™ software is a block diagram modeling environment for the engineering design and simulation of rigid body machines and their motions, using the standard Newtonian dynamics of forces and torques Instead of representing a mathematical model of the system, we develop a representation that describes the key components of the mechanical system The base units in SimMechanics . appearance and use. Then in the second Applications of MATLAB in Science and Engineering 318 part, we discuss Simulink and MATLAB features useful for viewing and analyzing simulation results. In. number of errors, and the third is the number of bits tested. Finally, the BER is represented versus the signal-to-noise power ratio (Fig. 45). Applications of MATLAB in Science and Engineering. Direct Digital Synthesizers, Proceedings of XVIII Conference on Design of Circuits and Integrated Systems, pp. 73 7- 7 42, ISBN 8 4-8 70 8 7- 4 0-X, Ciudad Real, Spain, November, 2003. Simon, M.; Omura,