1 Thuan Xuan Nguyen Department of Electronics and Telecommunications University of Science, Ho Chi Minh City Vietnam National University, Ho Chi Minh City Tel: (+84) 906 834 817 Email: thuannguyen.teaching@gmail.com Site: http://www.thuanxuannguyen.tk/ ASSIGNMENT #6 Edited: Wednesday, May 18 th 2011 Question 1, 6: use Vietnamese only 1. Based on Section 7.9 (page 497/1003), express the differences in sequencing methodologies between Pentium 4 and Itanium 2. 2. Consider the path in the following figure using flip-flops F1, F2, and F3. The flip-flops have a setup time of 100 ps and a clock-to-Q delay of 150 ps. There is no skew between the clocks Φ1a, Φ1b, Φ1c that all share the same start time. The departure time from each flop is D1 = D2 = D3 = 0. o What is the minimum cycle time at which the system operates correctly? o Suppose that Φ1a and Φ1b are in a common local clock domain, but Φ1c is in a different clock domain. What is the minimum cycle time of the system if o The local skew is 50 ps and the global skew is 140 ps? o The local skew is 25 ps and the global skew is 300 ps? 3. For the path in Figure 3.1, determine which latches borrow time and if any setup time violations occur. Repeat for cycle times of 1200 and 800 ps. Assume there is zero clock skew and that the latch delays are accounted for in the propagation delay ∆’s. o ∆1 = 550 ps; ∆2 = 580 ps; ∆3 = 450 ps; ∆4 = 200 ps o ∆1 = 300 ps; ∆2 = 600 ps; ∆3 = 400 ps; ∆4 = 550 ps 2 Figure 3.1 4. Determine the minimum clock period at which the circuit in Figure 4.1 will operate correctly for each of the following logic delays. Assume there is zero clock skew and that the latch delays are accounted for in the propagation delay ∆’s. o ∆1 = 300 ps; ∆2 = 400 ps; ∆3 = 200 ps; ∆4 = 350 ps o ∆1 = 300 ps; ∆2 = 900 ps; ∆3 = 200 ps; ∆4 = 350 ps Figure 4.1 5. A synchronizer users a flip-flop with T s = 54 ps and T 0 = 21 ps. Assuming the input toggles at 10 MHz and the setup time is negligible, what is the minimum clock period for which the mean time between failures exceeds 100 years? 6. Inferior Circuits, Inc., wants to sell you a perfect synchronizer that they claim never produces a metastable output. The synchronizer consists of a regular flip-flop followed by a high-gain comparator that produces a high output for inputs above 0.25V DD and a low output for inputs below that point. The VP of marketing argues that even if the flip-flop enters metastability, its output will hover near V DD /2 so the synchronizer will produce a good high output after the comparator. Why wouldn’t you buy this synchronizer? . City Tel: (+84) 9 06 834 817 Email: thuannguyen.teaching@gmail.com Site: http://www.thuanxuannguyen.tk/ ASSIGNMENT #6 Edited: Wednesday, May 18 th 2011 Question 1, 6: use Vietnamese. 2. Consider the path in the following figure using flip-flops F1, F2, and F3. The flip-flops have a setup time of 100 ps and a clock-to-Q delay of 150 ps. There is no skew between the clocks Φ1a,. 6. Inferior Circuits, Inc., wants to sell you a perfect synchronizer that they claim never produces a metastable output. The synchronizer consists of a regular flip-flop followed by a high-gain