Introduction to CMOS VLSI Design Design for Low Power Outline     Power and Energy Dynamic Power Static Power Low Power Design CMOS VLSI Design Design for LowSlide Power Power and Energy  Power is drawn from a voltage source attached to the VDD pin(s) of a chip  Instantaneous Power: P(t ) = iDD (t )VDD T  Energy:  Average Power: T E = ∫ P(t )dt = ∫ iDD (t )VDD dt T Pavg E = = ∫ iDD (t )VDD dt T T CMOS VLSI Design Design for LowSlide Power Dynamic Power  Dynamic power is required to charge and discharge load capacitances when transistors switch     One cycle involves a rising and falling output On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND VDD This repeats Tfsw times iDD(t) over an interval of T fsw CMOS VLSI Design C Design for LowSlide Power Dynamic Power Cont Pdynamic = VDD iDD(t) fsw CMOS VLSI Design C Design for LowSlide Power Dynamic Power Cont T Pdynamic = ∫ iDD (t )VDD dt T T VDD = ∫ iDD (t )dt T VDD = [ TfswCVDD ] T = CVDD f sw VDD iDD(t) fsw CMOS VLSI Design C Design for LowSlide Power Activity Factor  Suppose the system clock frequency = f  Let fsw = αf, where α = activity factor – If the signal is a clock, α = – If the signal switches once per cycle, α = ẵ Dynamic gates: ã Switch either or times per cycle, α = ½ – Static gates: • Depends on design, but typically α = 0.1  Dynamic power: Pdynamic = α CVDD f CMOS VLSI Design Design for LowSlide Power Short Circuit Current  When transistors switch, both nMOS and pMOS networks may be momentarily ON at once  Leads to a blip of “short circuit” current  < 10% of dynamic power if rise/fall times are comparable for input and output CMOS VLSI Design Design for LowSlide Power Example  200 Mtransistor chip – 20M logic transistors • Average width: 12 λ – 180M memory transistors • Average width: λ – 1.2 V 100 nm process – Cg = fF/µm CMOS VLSI Design Design for LowSlide Power Dynamic Example  Static CMOS logic gates: activity factor = 0.1  Memory arrays: activity factor = 0.05 (many banks!)  Estimate dynamic power consumption per MHz Neglect wire capacitance and short-circuit current CMOS VLSI Design Design for Low Power Slide 10 Dynamic Example  Static CMOS logic gates: activity factor = 0.1  Memory arrays: activity factor = 0.05 (many banks!)  Estimate dynamic power consumption per MHz Neglect wire capacitance Clogic = ( 20 × 106 ) ( 12λ ) ( 0.05µm / λ ) ( fF / µm ) = 24nF Cmem = ( 180 × 106 ) ( 4λ ) ( 0.05µ m / λ ) ( fF / µ m ) = 72nF Pdynamic = 0.1Clogic + 0.05Cmem  ( 1.2 ) f = 8.6 mW/MHz   CMOS VLSI Design Design for Low Power Slide 11 Static Power  Static power is consumed even when chip is quiescent – Ratioed circuits burn power in fight between ON transistors – Leakage draws power from nominally OFF devices Vgs −Vt I ds = I ds 0e nvT −Vds   vT 1 − e      Vt = Vt − ηVds + γ ( φs + Vsb − φs CMOS VLSI Design ) Design for Low Power Slide 12 Ratio Example  The chip contains a 32 word x 48 bit ROM – Uses pseudo-nMOS decoder and bitline pullups – On average, one wordline and 24 bitlines are high  Find static power drawn by the ROM – β = 75 µA/V2 – Vtp = -0.4V CMOS VLSI Design Design for Low Power Slide 13 Ratio Example  The chip contains a 32 word x 48 bit ROM – Uses pseudo-nMOS decoder and bitline pullups – On average, one wordline and 24 bitlines are high  Find static power drawn by the ROM – β = 75 µA/V2 – Vtp = -0.4V  Solution: ( VDD − Vtp ) I pull-up = β = 24μA Ppull-up = VDD I pull-up = 29μW Pstatic = (31 + 24) Ppull-up = 1.6 mW CMOS VLSI Design Design for Low Power Slide 14 Leakage Example  The process has two threshold voltages and two oxide thicknesses  Subthreshold leakage: – 20 nA/µm for low Vt – 0.02 nA/µm for high Vt  Gate leakage: – nA/µm for thin oxide – 0.002 nA/µm for thick oxide  Memories use low-leakage transistors everywhere  Gates use low-leakage transistors on 80% of logic CMOS VLSI Design Design for Low Power Slide 15 Leakage Example Cont  Estimate static power: CMOS VLSI Design Design for Low Power Slide 16 Leakage Example Cont  Estimate static power: – High leakage: ( 20 × 106 ) ( 0.2 ) ( 12λ ) ( 0.05µm / λ ) = 2.4 ì 106 m Low leakage: ( 20 × 106 ) ( 0.8) ( 12λ ) ( 0.05àm / ) + ( 180 ì 106 ) ( 4λ ) ( 0.05µm / λ ) = 45.6 × 106 µm I static = ( 2.4 × 106 µ m ) ( 20nA / µ m ) / + ( 3nA / µm )  +  ( 45.6 ì 10 àm ) ( 0.02nA / µm ) / + ( 0.002nA / µm )    Pstatic = 32mA = I staticVDD = 38mW CMOS VLSI Design Design for Low Power Slide 17 Leakage Example Cont  Estimate static power: – High leakage: ( 20 × 106 ) ( 0.2 ) ( 12 ) ( 0.05àm / ) = 2.4 ì 106 m Low leakage: ( 20 ì 106 ) ( 0.8) ( 12λ ) ( 0.05µm / λ ) + ( 180 × 106 ) ( 4λ ) ( 0.05àm / ) = 45.6 ì 106 àm I static = ( 2.4 ì 106 m ) ( 20nA / µ m ) / + ( 3nA / µm )  +   ( 45.6 × 10 µm ) ( 0.02nA / µm ) / + ( 0.002nA / µm )    Pstatic = 32mA = I staticVDD = 38mW  If no low leakage devices, Pstatic = 749 mW (!) CMOS VLSI Design Design for Low Power Slide 18 Low Power Design  Reduce dynamic power – α: – C: – VDD: – f:  Reduce static power CMOS VLSI Design Design for Low Power Slide 19 Low Power Design  Reduce dynamic power – α: clock gating, sleep mode – C: – VDD: – f:  Reduce static power CMOS VLSI Design Design for Low Power Slide 20 Low Power Design  Reduce dynamic power – α: clock gating, sleep mode – C: small transistors (esp on clock), short wires – VDD: – f:  Reduce static power CMOS VLSI Design Design for Low Power Slide 21 Low Power Design  Reduce dynamic power – α: clock gating, sleep mode – C: small transistors (esp on clock), short wires – VDD: lowest suitable voltage – f:  Reduce static power CMOS VLSI Design Design for Low Power Slide 22 Low Power Design  Reduce dynamic power – α: clock gating, sleep mode – C: small transistors (esp on clock), short wires – VDD: lowest suitable voltage – f: lowest suitable frequency  Reduce static power CMOS VLSI Design Design for Low Power Slide 23 Low Power Design  Reduce dynamic power – α: clock gating, sleep mode – C: small transistors (esp on clock), short wires – VDD: lowest suitable voltage – f: lowest suitable frequency  Reduce static power – Selectively use ratioed circuits – Selectively use low Vt devices – Leakage reduction: stacked devices, body bias, low temperature CMOS VLSI Design Design for Low Power Slide 24 ... Design for Low Power Slide 19 Low Power Design  Reduce dynamic power – α: clock gating, sleep mode – C: – VDD: – f:  Reduce static power CMOS VLSI Design Design for Low Power Slide 20 Low Power Design. .. low leakage devices, Pstatic = 749 mW (!) CMOS VLSI Design Design for Low Power Slide 18 Low Power Design  Reduce dynamic power – α: – C: – VDD: – f:  Reduce static power CMOS VLSI Design Design...Outline     Power and Energy Dynamic Power Static Power Low Power Design CMOS VLSI Design Design for LowSlide Power Power and Energy  Power is drawn from a voltage source